90 lines
2.2 KiB
C
90 lines
2.2 KiB
C
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#ifndef _ASM_X86_QSPINLOCK_H
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#define _ASM_X86_QSPINLOCK_H
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#include <asm/cpufeature.h>
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#include <asm-generic/qspinlock_types.h>
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#include <asm/paravirt.h>
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#include <asm/rmwcc.h>
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#define _Q_PENDING_LOOPS (1 << 9)
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#define queued_fetch_set_pending_acquire queued_fetch_set_pending_acquire
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static __always_inline bool __queued_RMW_btsl(struct qspinlock *lock)
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{
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GEN_BINARY_RMWcc(LOCK_PREFIX "btsl", lock->val.counter,
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"I", _Q_PENDING_OFFSET, "%0", c);
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}
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static __always_inline u32 queued_fetch_set_pending_acquire(struct qspinlock *lock)
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{
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u32 val = 0;
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if (__queued_RMW_btsl(lock))
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val |= _Q_PENDING_VAL;
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val |= atomic_read(&lock->val) & ~_Q_PENDING_MASK;
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return val;
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}
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#define queued_spin_unlock queued_spin_unlock
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/**
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* queued_spin_unlock - release a queued spinlock
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* @lock : Pointer to queued spinlock structure
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*
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* A smp_store_release() on the least-significant byte.
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*/
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static inline void native_queued_spin_unlock(struct qspinlock *lock)
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{
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smp_store_release(&lock->locked, 0);
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}
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#ifdef CONFIG_PARAVIRT_SPINLOCKS
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extern void native_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val);
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extern void __pv_init_lock_hash(void);
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extern void __pv_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val);
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extern void __raw_callee_save___pv_queued_spin_unlock(struct qspinlock *lock);
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static inline void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val)
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{
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pv_queued_spin_lock_slowpath(lock, val);
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}
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static inline void queued_spin_unlock(struct qspinlock *lock)
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{
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pv_queued_spin_unlock(lock);
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}
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#else
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static inline void queued_spin_unlock(struct qspinlock *lock)
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{
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native_queued_spin_unlock(lock);
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}
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#endif
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#ifdef CONFIG_PARAVIRT
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#define virt_spin_lock virt_spin_lock
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static inline bool virt_spin_lock(struct qspinlock *lock)
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{
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if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
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return false;
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/*
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* On hypervisors without PARAVIRT_SPINLOCKS support we fall
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* back to a Test-and-Set spinlock, because fair locks have
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* horrible lock 'holder' preemption issues.
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*/
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do {
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while (atomic_read(&lock->val) != 0)
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cpu_relax();
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} while (atomic_cmpxchg(&lock->val, 0, _Q_LOCKED_VAL) != 0);
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return true;
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}
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#endif /* CONFIG_PARAVIRT */
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#include <asm-generic/qspinlock.h>
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#endif /* _ASM_X86_QSPINLOCK_H */
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