627 lines
14 KiB
C
627 lines
14 KiB
C
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/*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/at91_pmc.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include "pmc.h"
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#define SLOW_CLOCK_FREQ 32768
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#define MAINF_DIV 16
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#define MAINFRDY_TIMEOUT (((MAINF_DIV + 1) * USEC_PER_SEC) / \
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SLOW_CLOCK_FREQ)
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#define MAINF_LOOP_MIN_WAIT (USEC_PER_SEC / SLOW_CLOCK_FREQ)
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#define MAINF_LOOP_MAX_WAIT MAINFRDY_TIMEOUT
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#define MOR_KEY_MASK (0xff << 16)
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#define clk_main_parent_select(s) (((s) & \
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(AT91_PMC_MOSCEN | \
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AT91_PMC_OSCBYPASS)) ? 1 : 0)
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struct clk_main_osc {
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struct clk_hw hw;
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struct regmap *regmap;
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};
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#define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw)
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struct clk_main_rc_osc {
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struct clk_hw hw;
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struct regmap *regmap;
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unsigned long frequency;
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unsigned long accuracy;
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};
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#define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw)
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struct clk_rm9200_main {
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struct clk_hw hw;
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struct regmap *regmap;
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};
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#define to_clk_rm9200_main(hw) container_of(hw, struct clk_rm9200_main, hw)
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struct clk_sam9x5_main {
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struct clk_hw hw;
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struct regmap *regmap;
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u8 parent;
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};
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#define to_clk_sam9x5_main(hw) container_of(hw, struct clk_sam9x5_main, hw)
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static inline bool clk_main_osc_ready(struct regmap *regmap)
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{
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unsigned int status;
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regmap_read(regmap, AT91_PMC_SR, &status);
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return status & AT91_PMC_MOSCS;
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}
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static int clk_main_osc_prepare(struct clk_hw *hw)
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{
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struct clk_main_osc *osc = to_clk_main_osc(hw);
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struct regmap *regmap = osc->regmap;
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u32 tmp;
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regmap_read(regmap, AT91_CKGR_MOR, &tmp);
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tmp &= ~MOR_KEY_MASK;
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if (tmp & AT91_PMC_OSCBYPASS)
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return 0;
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if (!(tmp & AT91_PMC_MOSCEN)) {
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tmp |= AT91_PMC_MOSCEN | AT91_PMC_KEY;
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regmap_write(regmap, AT91_CKGR_MOR, tmp);
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}
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while (!clk_main_osc_ready(regmap))
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cpu_relax();
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return 0;
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}
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static void clk_main_osc_unprepare(struct clk_hw *hw)
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{
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struct clk_main_osc *osc = to_clk_main_osc(hw);
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struct regmap *regmap = osc->regmap;
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u32 tmp;
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regmap_read(regmap, AT91_CKGR_MOR, &tmp);
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if (tmp & AT91_PMC_OSCBYPASS)
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return;
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if (!(tmp & AT91_PMC_MOSCEN))
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return;
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tmp &= ~(AT91_PMC_KEY | AT91_PMC_MOSCEN);
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regmap_write(regmap, AT91_CKGR_MOR, tmp | AT91_PMC_KEY);
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}
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static int clk_main_osc_is_prepared(struct clk_hw *hw)
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{
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struct clk_main_osc *osc = to_clk_main_osc(hw);
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struct regmap *regmap = osc->regmap;
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u32 tmp, status;
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regmap_read(regmap, AT91_CKGR_MOR, &tmp);
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if (tmp & AT91_PMC_OSCBYPASS)
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return 1;
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regmap_read(regmap, AT91_PMC_SR, &status);
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return (status & AT91_PMC_MOSCS) && clk_main_parent_select(tmp);
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}
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static const struct clk_ops main_osc_ops = {
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.prepare = clk_main_osc_prepare,
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.unprepare = clk_main_osc_unprepare,
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.is_prepared = clk_main_osc_is_prepared,
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};
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static struct clk_hw * __init
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at91_clk_register_main_osc(struct regmap *regmap,
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const char *name,
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const char *parent_name,
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bool bypass)
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{
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struct clk_main_osc *osc;
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struct clk_init_data init;
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struct clk_hw *hw;
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int ret;
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if (!name || !parent_name)
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return ERR_PTR(-EINVAL);
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osc = kzalloc(sizeof(*osc), GFP_KERNEL);
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if (!osc)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &main_osc_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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init.flags = CLK_IGNORE_UNUSED;
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osc->hw.init = &init;
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osc->regmap = regmap;
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if (bypass)
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regmap_update_bits(regmap,
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AT91_CKGR_MOR, MOR_KEY_MASK |
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AT91_PMC_OSCBYPASS,
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AT91_PMC_OSCBYPASS | AT91_PMC_KEY);
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hw = &osc->hw;
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ret = clk_hw_register(NULL, &osc->hw);
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if (ret) {
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kfree(osc);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np)
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{
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struct clk_hw *hw;
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const char *name = np->name;
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const char *parent_name;
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struct regmap *regmap;
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bool bypass;
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of_property_read_string(np, "clock-output-names", &name);
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bypass = of_property_read_bool(np, "atmel,osc-bypass");
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parent_name = of_clk_get_parent_name(np, 0);
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regmap = syscon_node_to_regmap(of_get_parent(np));
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if (IS_ERR(regmap))
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return;
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hw = at91_clk_register_main_osc(regmap, name, parent_name, bypass);
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if (IS_ERR(hw))
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return;
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of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
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}
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CLK_OF_DECLARE(at91rm9200_clk_main_osc, "atmel,at91rm9200-clk-main-osc",
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of_at91rm9200_clk_main_osc_setup);
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static bool clk_main_rc_osc_ready(struct regmap *regmap)
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{
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unsigned int status;
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regmap_read(regmap, AT91_PMC_SR, &status);
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return status & AT91_PMC_MOSCRCS;
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}
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static int clk_main_rc_osc_prepare(struct clk_hw *hw)
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{
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struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
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struct regmap *regmap = osc->regmap;
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unsigned int mor;
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regmap_read(regmap, AT91_CKGR_MOR, &mor);
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if (!(mor & AT91_PMC_MOSCRCEN))
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regmap_update_bits(regmap, AT91_CKGR_MOR,
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MOR_KEY_MASK | AT91_PMC_MOSCRCEN,
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AT91_PMC_MOSCRCEN | AT91_PMC_KEY);
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while (!clk_main_rc_osc_ready(regmap))
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cpu_relax();
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return 0;
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}
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static void clk_main_rc_osc_unprepare(struct clk_hw *hw)
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{
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struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
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struct regmap *regmap = osc->regmap;
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unsigned int mor;
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regmap_read(regmap, AT91_CKGR_MOR, &mor);
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if (!(mor & AT91_PMC_MOSCRCEN))
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return;
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regmap_update_bits(regmap, AT91_CKGR_MOR,
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MOR_KEY_MASK | AT91_PMC_MOSCRCEN, AT91_PMC_KEY);
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}
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static int clk_main_rc_osc_is_prepared(struct clk_hw *hw)
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{
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struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
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struct regmap *regmap = osc->regmap;
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unsigned int mor, status;
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regmap_read(regmap, AT91_CKGR_MOR, &mor);
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regmap_read(regmap, AT91_PMC_SR, &status);
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return (mor & AT91_PMC_MOSCRCEN) && (status & AT91_PMC_MOSCRCS);
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}
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static unsigned long clk_main_rc_osc_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
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return osc->frequency;
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}
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static unsigned long clk_main_rc_osc_recalc_accuracy(struct clk_hw *hw,
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unsigned long parent_acc)
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{
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struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
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return osc->accuracy;
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}
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static const struct clk_ops main_rc_osc_ops = {
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.prepare = clk_main_rc_osc_prepare,
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.unprepare = clk_main_rc_osc_unprepare,
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.is_prepared = clk_main_rc_osc_is_prepared,
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.recalc_rate = clk_main_rc_osc_recalc_rate,
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.recalc_accuracy = clk_main_rc_osc_recalc_accuracy,
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};
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static struct clk_hw * __init
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at91_clk_register_main_rc_osc(struct regmap *regmap,
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const char *name,
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u32 frequency, u32 accuracy)
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{
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struct clk_main_rc_osc *osc;
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struct clk_init_data init;
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struct clk_hw *hw;
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int ret;
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if (!name || !frequency)
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return ERR_PTR(-EINVAL);
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osc = kzalloc(sizeof(*osc), GFP_KERNEL);
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if (!osc)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &main_rc_osc_ops;
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init.parent_names = NULL;
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init.num_parents = 0;
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init.flags = CLK_IGNORE_UNUSED;
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osc->hw.init = &init;
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osc->regmap = regmap;
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osc->frequency = frequency;
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osc->accuracy = accuracy;
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hw = &osc->hw;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(osc);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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static void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np)
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{
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struct clk_hw *hw;
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u32 frequency = 0;
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u32 accuracy = 0;
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const char *name = np->name;
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struct regmap *regmap;
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of_property_read_string(np, "clock-output-names", &name);
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of_property_read_u32(np, "clock-frequency", &frequency);
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of_property_read_u32(np, "clock-accuracy", &accuracy);
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regmap = syscon_node_to_regmap(of_get_parent(np));
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if (IS_ERR(regmap))
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return;
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hw = at91_clk_register_main_rc_osc(regmap, name, frequency, accuracy);
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if (IS_ERR(hw))
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return;
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of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
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}
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CLK_OF_DECLARE(at91sam9x5_clk_main_rc_osc, "atmel,at91sam9x5-clk-main-rc-osc",
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of_at91sam9x5_clk_main_rc_osc_setup);
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static int clk_main_probe_frequency(struct regmap *regmap)
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{
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unsigned long prep_time, timeout;
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unsigned int mcfr;
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timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT);
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do {
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prep_time = jiffies;
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regmap_read(regmap, AT91_CKGR_MCFR, &mcfr);
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if (mcfr & AT91_PMC_MAINRDY)
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return 0;
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if (system_state < SYSTEM_RUNNING)
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udelay(MAINF_LOOP_MIN_WAIT);
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else
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usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT);
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} while (time_before(prep_time, timeout));
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return -ETIMEDOUT;
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}
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static unsigned long clk_main_recalc_rate(struct regmap *regmap,
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unsigned long parent_rate)
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{
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unsigned int mcfr;
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if (parent_rate)
|
||
|
|
return parent_rate;
|
||
|
|
|
||
|
|
pr_warn("Main crystal frequency not set, using approximate value\n");
|
||
|
|
regmap_read(regmap, AT91_CKGR_MCFR, &mcfr);
|
||
|
|
if (!(mcfr & AT91_PMC_MAINRDY))
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
return ((mcfr & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int clk_rm9200_main_prepare(struct clk_hw *hw)
|
||
|
|
{
|
||
|
|
struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
|
||
|
|
|
||
|
|
return clk_main_probe_frequency(clkmain->regmap);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int clk_rm9200_main_is_prepared(struct clk_hw *hw)
|
||
|
|
{
|
||
|
|
struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
|
||
|
|
unsigned int status;
|
||
|
|
|
||
|
|
regmap_read(clkmain->regmap, AT91_CKGR_MCFR, &status);
|
||
|
|
|
||
|
|
return status & AT91_PMC_MAINRDY ? 1 : 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static unsigned long clk_rm9200_main_recalc_rate(struct clk_hw *hw,
|
||
|
|
unsigned long parent_rate)
|
||
|
|
{
|
||
|
|
struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
|
||
|
|
|
||
|
|
return clk_main_recalc_rate(clkmain->regmap, parent_rate);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct clk_ops rm9200_main_ops = {
|
||
|
|
.prepare = clk_rm9200_main_prepare,
|
||
|
|
.is_prepared = clk_rm9200_main_is_prepared,
|
||
|
|
.recalc_rate = clk_rm9200_main_recalc_rate,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct clk_hw * __init
|
||
|
|
at91_clk_register_rm9200_main(struct regmap *regmap,
|
||
|
|
const char *name,
|
||
|
|
const char *parent_name)
|
||
|
|
{
|
||
|
|
struct clk_rm9200_main *clkmain;
|
||
|
|
struct clk_init_data init;
|
||
|
|
struct clk_hw *hw;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
if (!name)
|
||
|
|
return ERR_PTR(-EINVAL);
|
||
|
|
|
||
|
|
if (!parent_name)
|
||
|
|
return ERR_PTR(-EINVAL);
|
||
|
|
|
||
|
|
clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
|
||
|
|
if (!clkmain)
|
||
|
|
return ERR_PTR(-ENOMEM);
|
||
|
|
|
||
|
|
init.name = name;
|
||
|
|
init.ops = &rm9200_main_ops;
|
||
|
|
init.parent_names = &parent_name;
|
||
|
|
init.num_parents = 1;
|
||
|
|
init.flags = 0;
|
||
|
|
|
||
|
|
clkmain->hw.init = &init;
|
||
|
|
clkmain->regmap = regmap;
|
||
|
|
|
||
|
|
hw = &clkmain->hw;
|
||
|
|
ret = clk_hw_register(NULL, &clkmain->hw);
|
||
|
|
if (ret) {
|
||
|
|
kfree(clkmain);
|
||
|
|
hw = ERR_PTR(ret);
|
||
|
|
}
|
||
|
|
|
||
|
|
return hw;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
|
||
|
|
{
|
||
|
|
struct clk_hw *hw;
|
||
|
|
const char *parent_name;
|
||
|
|
const char *name = np->name;
|
||
|
|
struct regmap *regmap;
|
||
|
|
|
||
|
|
parent_name = of_clk_get_parent_name(np, 0);
|
||
|
|
of_property_read_string(np, "clock-output-names", &name);
|
||
|
|
|
||
|
|
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||
|
|
if (IS_ERR(regmap))
|
||
|
|
return;
|
||
|
|
|
||
|
|
hw = at91_clk_register_rm9200_main(regmap, name, parent_name);
|
||
|
|
if (IS_ERR(hw))
|
||
|
|
return;
|
||
|
|
|
||
|
|
of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
|
||
|
|
}
|
||
|
|
CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main",
|
||
|
|
of_at91rm9200_clk_main_setup);
|
||
|
|
|
||
|
|
static inline bool clk_sam9x5_main_ready(struct regmap *regmap)
|
||
|
|
{
|
||
|
|
unsigned int status;
|
||
|
|
|
||
|
|
regmap_read(regmap, AT91_PMC_SR, &status);
|
||
|
|
|
||
|
|
return status & AT91_PMC_MOSCSELS ? 1 : 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int clk_sam9x5_main_prepare(struct clk_hw *hw)
|
||
|
|
{
|
||
|
|
struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
|
||
|
|
struct regmap *regmap = clkmain->regmap;
|
||
|
|
|
||
|
|
while (!clk_sam9x5_main_ready(regmap))
|
||
|
|
cpu_relax();
|
||
|
|
|
||
|
|
return clk_main_probe_frequency(regmap);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int clk_sam9x5_main_is_prepared(struct clk_hw *hw)
|
||
|
|
{
|
||
|
|
struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
|
||
|
|
|
||
|
|
return clk_sam9x5_main_ready(clkmain->regmap);
|
||
|
|
}
|
||
|
|
|
||
|
|
static unsigned long clk_sam9x5_main_recalc_rate(struct clk_hw *hw,
|
||
|
|
unsigned long parent_rate)
|
||
|
|
{
|
||
|
|
struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
|
||
|
|
|
||
|
|
return clk_main_recalc_rate(clkmain->regmap, parent_rate);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int clk_sam9x5_main_set_parent(struct clk_hw *hw, u8 index)
|
||
|
|
{
|
||
|
|
struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
|
||
|
|
struct regmap *regmap = clkmain->regmap;
|
||
|
|
unsigned int tmp;
|
||
|
|
|
||
|
|
if (index > 1)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
regmap_read(regmap, AT91_CKGR_MOR, &tmp);
|
||
|
|
|
||
|
|
if (index && !(tmp & AT91_PMC_MOSCSEL))
|
||
|
|
tmp = AT91_PMC_MOSCSEL;
|
||
|
|
else if (!index && (tmp & AT91_PMC_MOSCSEL))
|
||
|
|
tmp = 0;
|
||
|
|
else
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
regmap_update_bits(regmap, AT91_CKGR_MOR,
|
||
|
|
AT91_PMC_MOSCSEL | MOR_KEY_MASK,
|
||
|
|
tmp | AT91_PMC_KEY);
|
||
|
|
|
||
|
|
while (!clk_sam9x5_main_ready(regmap))
|
||
|
|
cpu_relax();
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw)
|
||
|
|
{
|
||
|
|
struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
|
||
|
|
unsigned int status;
|
||
|
|
|
||
|
|
regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
|
||
|
|
|
||
|
|
return clk_main_parent_select(status);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct clk_ops sam9x5_main_ops = {
|
||
|
|
.prepare = clk_sam9x5_main_prepare,
|
||
|
|
.is_prepared = clk_sam9x5_main_is_prepared,
|
||
|
|
.recalc_rate = clk_sam9x5_main_recalc_rate,
|
||
|
|
.set_parent = clk_sam9x5_main_set_parent,
|
||
|
|
.get_parent = clk_sam9x5_main_get_parent,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct clk_hw * __init
|
||
|
|
at91_clk_register_sam9x5_main(struct regmap *regmap,
|
||
|
|
const char *name,
|
||
|
|
const char **parent_names,
|
||
|
|
int num_parents)
|
||
|
|
{
|
||
|
|
struct clk_sam9x5_main *clkmain;
|
||
|
|
struct clk_init_data init;
|
||
|
|
unsigned int status;
|
||
|
|
struct clk_hw *hw;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
if (!name)
|
||
|
|
return ERR_PTR(-EINVAL);
|
||
|
|
|
||
|
|
if (!parent_names || !num_parents)
|
||
|
|
return ERR_PTR(-EINVAL);
|
||
|
|
|
||
|
|
clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
|
||
|
|
if (!clkmain)
|
||
|
|
return ERR_PTR(-ENOMEM);
|
||
|
|
|
||
|
|
init.name = name;
|
||
|
|
init.ops = &sam9x5_main_ops;
|
||
|
|
init.parent_names = parent_names;
|
||
|
|
init.num_parents = num_parents;
|
||
|
|
init.flags = CLK_SET_PARENT_GATE;
|
||
|
|
|
||
|
|
clkmain->hw.init = &init;
|
||
|
|
clkmain->regmap = regmap;
|
||
|
|
regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
|
||
|
|
clkmain->parent = clk_main_parent_select(status);
|
||
|
|
|
||
|
|
hw = &clkmain->hw;
|
||
|
|
ret = clk_hw_register(NULL, &clkmain->hw);
|
||
|
|
if (ret) {
|
||
|
|
kfree(clkmain);
|
||
|
|
hw = ERR_PTR(ret);
|
||
|
|
}
|
||
|
|
|
||
|
|
return hw;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void __init of_at91sam9x5_clk_main_setup(struct device_node *np)
|
||
|
|
{
|
||
|
|
struct clk_hw *hw;
|
||
|
|
const char *parent_names[2];
|
||
|
|
unsigned int num_parents;
|
||
|
|
const char *name = np->name;
|
||
|
|
struct regmap *regmap;
|
||
|
|
|
||
|
|
num_parents = of_clk_get_parent_count(np);
|
||
|
|
if (num_parents == 0 || num_parents > 2)
|
||
|
|
return;
|
||
|
|
|
||
|
|
of_clk_parent_fill(np, parent_names, num_parents);
|
||
|
|
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||
|
|
if (IS_ERR(regmap))
|
||
|
|
return;
|
||
|
|
|
||
|
|
of_property_read_string(np, "clock-output-names", &name);
|
||
|
|
|
||
|
|
hw = at91_clk_register_sam9x5_main(regmap, name, parent_names,
|
||
|
|
num_parents);
|
||
|
|
if (IS_ERR(hw))
|
||
|
|
return;
|
||
|
|
|
||
|
|
of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
|
||
|
|
}
|
||
|
|
CLK_OF_DECLARE(at91sam9x5_clk_main, "atmel,at91sam9x5-clk-main",
|
||
|
|
of_at91sam9x5_clk_main_setup);
|