192 lines
6.0 KiB
C
192 lines
6.0 KiB
C
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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* The full GNU General Public License is included in this distribution
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* in the file called COPYING.
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*
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* BSD LICENSE
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*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/init.h>
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#include <dt-bindings/clock/gxbb-aoclkc.h>
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#include <dt-bindings/reset/gxbb-aoclkc.h>
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static DEFINE_SPINLOCK(gxbb_aoclk_lock);
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struct gxbb_aoclk_reset_controller {
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struct reset_controller_dev reset;
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unsigned int *data;
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void __iomem *base;
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};
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static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct gxbb_aoclk_reset_controller *reset =
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container_of(rcdev, struct gxbb_aoclk_reset_controller, reset);
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writel(BIT(reset->data[id]), reset->base);
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return 0;
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}
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static const struct reset_control_ops gxbb_aoclk_reset_ops = {
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.reset = gxbb_aoclk_do_reset,
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};
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#define GXBB_AO_GATE(_name, _bit) \
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static struct clk_gate _name##_ao = { \
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.reg = (void __iomem *)0, \
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.bit_idx = (_bit), \
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.lock = &gxbb_aoclk_lock, \
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.hw.init = &(struct clk_init_data) { \
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.name = #_name "_ao", \
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.ops = &clk_gate_ops, \
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.parent_names = (const char *[]){ "clk81" }, \
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.num_parents = 1, \
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.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
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}, \
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}
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GXBB_AO_GATE(remote, 0);
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GXBB_AO_GATE(i2c_master, 1);
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GXBB_AO_GATE(i2c_slave, 2);
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GXBB_AO_GATE(uart1, 3);
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GXBB_AO_GATE(uart2, 5);
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GXBB_AO_GATE(ir_blaster, 6);
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static unsigned int gxbb_aoclk_reset[] = {
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[RESET_AO_REMOTE] = 16,
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[RESET_AO_I2C_MASTER] = 18,
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[RESET_AO_I2C_SLAVE] = 19,
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[RESET_AO_UART1] = 17,
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[RESET_AO_UART2] = 22,
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[RESET_AO_IR_BLASTER] = 23,
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};
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static struct clk_gate *gxbb_aoclk_gate[] = {
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[CLKID_AO_REMOTE] = &remote_ao,
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[CLKID_AO_I2C_MASTER] = &i2c_master_ao,
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[CLKID_AO_I2C_SLAVE] = &i2c_slave_ao,
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[CLKID_AO_UART1] = &uart1_ao,
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[CLKID_AO_UART2] = &uart2_ao,
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[CLKID_AO_IR_BLASTER] = &ir_blaster_ao,
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};
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static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
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.hws = {
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[CLKID_AO_REMOTE] = &remote_ao.hw,
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[CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
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[CLKID_AO_I2C_SLAVE] = &i2c_slave_ao.hw,
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[CLKID_AO_UART1] = &uart1_ao.hw,
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[CLKID_AO_UART2] = &uart2_ao.hw,
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[CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
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},
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.num = ARRAY_SIZE(gxbb_aoclk_gate),
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};
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static int gxbb_aoclkc_probe(struct platform_device *pdev)
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{
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struct resource *res;
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void __iomem *base;
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int ret, clkid;
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struct device *dev = &pdev->dev;
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struct gxbb_aoclk_reset_controller *rstc;
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rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
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if (!rstc)
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return -ENOMEM;
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/* Generic clocks */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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/* Reset Controller */
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rstc->base = base;
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rstc->data = gxbb_aoclk_reset;
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rstc->reset.ops = &gxbb_aoclk_reset_ops;
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rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);
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rstc->reset.of_node = dev->of_node;
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ret = devm_reset_controller_register(dev, &rstc->reset);
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/*
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* Populate base address and register all clks
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*/
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for (clkid = 0; clkid < gxbb_aoclk_onecell_data.num; clkid++) {
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gxbb_aoclk_gate[clkid]->reg = base;
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ret = devm_clk_hw_register(dev,
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gxbb_aoclk_onecell_data.hws[clkid]);
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if (ret)
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return ret;
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}
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return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
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&gxbb_aoclk_onecell_data);
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}
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static const struct of_device_id gxbb_aoclkc_match_table[] = {
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{ .compatible = "amlogic,gxbb-aoclkc" },
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{ }
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};
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static struct platform_driver gxbb_aoclkc_driver = {
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.probe = gxbb_aoclkc_probe,
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.driver = {
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.name = "gxbb-aoclkc",
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.of_match_table = gxbb_aoclkc_match_table,
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},
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};
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builtin_platform_driver(gxbb_aoclkc_driver);
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