316 lines
8.5 KiB
C
316 lines
8.5 KiB
C
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/*
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* MVEBU Core divider clock
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*
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* Copyright (C) 2013 Marvell
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*
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* Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include "common.h"
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#define CORE_CLK_DIV_RATIO_MASK 0xff
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/*
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* This structure describes the hardware details (bit offset and mask)
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* to configure one particular core divider clock. Those hardware
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* details may differ from one SoC to another. This structure is
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* therefore typically instantiated statically to describe the
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* hardware details.
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*/
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struct clk_corediv_desc {
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unsigned int mask;
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unsigned int offset;
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unsigned int fieldbit;
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};
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/*
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* This structure describes the hardware details to configure the core
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* divider clocks on a given SoC. Amongst others, it points to the
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* array of core divider clock descriptors for this SoC, as well as
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* the corresponding operations to manipulate them.
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*/
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struct clk_corediv_soc_desc {
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const struct clk_corediv_desc *descs;
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unsigned int ndescs;
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const struct clk_ops ops;
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u32 ratio_reload;
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u32 enable_bit_offset;
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u32 ratio_offset;
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};
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/*
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* This structure represents one core divider clock for the clock
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* framework, and is dynamically allocated for each core divider clock
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* existing in the current SoC.
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*/
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struct clk_corediv {
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struct clk_hw hw;
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void __iomem *reg;
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const struct clk_corediv_desc *desc;
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const struct clk_corediv_soc_desc *soc_desc;
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spinlock_t lock;
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};
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static struct clk_onecell_data clk_data;
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/*
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* Description of the core divider clocks available. For now, we
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* support only NAND, and it is available at the same register
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* locations regardless of the SoC.
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*/
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static const struct clk_corediv_desc mvebu_corediv_desc[] = {
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{ .mask = 0x3f, .offset = 8, .fieldbit = 1 }, /* NAND clock */
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};
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#define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)
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static int clk_corediv_is_enabled(struct clk_hw *hwclk)
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{
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struct clk_corediv *corediv = to_corediv_clk(hwclk);
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const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;
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const struct clk_corediv_desc *desc = corediv->desc;
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u32 enable_mask = BIT(desc->fieldbit) << soc_desc->enable_bit_offset;
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return !!(readl(corediv->reg) & enable_mask);
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}
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static int clk_corediv_enable(struct clk_hw *hwclk)
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{
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struct clk_corediv *corediv = to_corediv_clk(hwclk);
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const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;
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const struct clk_corediv_desc *desc = corediv->desc;
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unsigned long flags = 0;
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u32 reg;
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spin_lock_irqsave(&corediv->lock, flags);
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reg = readl(corediv->reg);
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reg |= (BIT(desc->fieldbit) << soc_desc->enable_bit_offset);
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writel(reg, corediv->reg);
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spin_unlock_irqrestore(&corediv->lock, flags);
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return 0;
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}
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static void clk_corediv_disable(struct clk_hw *hwclk)
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{
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struct clk_corediv *corediv = to_corediv_clk(hwclk);
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const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;
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const struct clk_corediv_desc *desc = corediv->desc;
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unsigned long flags = 0;
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u32 reg;
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spin_lock_irqsave(&corediv->lock, flags);
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reg = readl(corediv->reg);
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reg &= ~(BIT(desc->fieldbit) << soc_desc->enable_bit_offset);
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writel(reg, corediv->reg);
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spin_unlock_irqrestore(&corediv->lock, flags);
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}
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static unsigned long clk_corediv_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct clk_corediv *corediv = to_corediv_clk(hwclk);
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const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;
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const struct clk_corediv_desc *desc = corediv->desc;
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u32 reg, div;
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reg = readl(corediv->reg + soc_desc->ratio_offset);
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div = (reg >> desc->offset) & desc->mask;
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return parent_rate / div;
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}
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static long clk_corediv_round_rate(struct clk_hw *hwclk, unsigned long rate,
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unsigned long *parent_rate)
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{
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/* Valid ratio are 1:4, 1:5, 1:6 and 1:8 */
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u32 div;
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div = *parent_rate / rate;
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if (div < 4)
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div = 4;
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else if (div > 6)
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div = 8;
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return *parent_rate / div;
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}
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static int clk_corediv_set_rate(struct clk_hw *hwclk, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_corediv *corediv = to_corediv_clk(hwclk);
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const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;
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const struct clk_corediv_desc *desc = corediv->desc;
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unsigned long flags = 0;
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u32 reg, div;
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div = parent_rate / rate;
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spin_lock_irqsave(&corediv->lock, flags);
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/* Write new divider to the divider ratio register */
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reg = readl(corediv->reg + soc_desc->ratio_offset);
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reg &= ~(desc->mask << desc->offset);
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reg |= (div & desc->mask) << desc->offset;
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writel(reg, corediv->reg + soc_desc->ratio_offset);
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/* Set reload-force for this clock */
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reg = readl(corediv->reg) | BIT(desc->fieldbit);
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writel(reg, corediv->reg);
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/* Now trigger the clock update */
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reg = readl(corediv->reg) | soc_desc->ratio_reload;
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writel(reg, corediv->reg);
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/*
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* Wait for clocks to settle down, and then clear all the
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* ratios request and the reload request.
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*/
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udelay(1000);
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reg &= ~(CORE_CLK_DIV_RATIO_MASK | soc_desc->ratio_reload);
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writel(reg, corediv->reg);
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udelay(1000);
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spin_unlock_irqrestore(&corediv->lock, flags);
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return 0;
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}
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static const struct clk_corediv_soc_desc armada370_corediv_soc = {
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.descs = mvebu_corediv_desc,
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.ndescs = ARRAY_SIZE(mvebu_corediv_desc),
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.ops = {
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.enable = clk_corediv_enable,
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.disable = clk_corediv_disable,
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.is_enabled = clk_corediv_is_enabled,
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.recalc_rate = clk_corediv_recalc_rate,
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.round_rate = clk_corediv_round_rate,
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.set_rate = clk_corediv_set_rate,
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},
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.ratio_reload = BIT(8),
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.enable_bit_offset = 24,
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.ratio_offset = 0x8,
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};
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static const struct clk_corediv_soc_desc armada380_corediv_soc = {
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.descs = mvebu_corediv_desc,
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.ndescs = ARRAY_SIZE(mvebu_corediv_desc),
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.ops = {
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.enable = clk_corediv_enable,
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.disable = clk_corediv_disable,
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.is_enabled = clk_corediv_is_enabled,
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.recalc_rate = clk_corediv_recalc_rate,
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.round_rate = clk_corediv_round_rate,
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.set_rate = clk_corediv_set_rate,
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},
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.ratio_reload = BIT(8),
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.enable_bit_offset = 16,
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.ratio_offset = 0x4,
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};
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static const struct clk_corediv_soc_desc armada375_corediv_soc = {
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.descs = mvebu_corediv_desc,
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.ndescs = ARRAY_SIZE(mvebu_corediv_desc),
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.ops = {
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.recalc_rate = clk_corediv_recalc_rate,
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.round_rate = clk_corediv_round_rate,
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.set_rate = clk_corediv_set_rate,
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},
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.ratio_reload = BIT(8),
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.ratio_offset = 0x4,
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};
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static void __init
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mvebu_corediv_clk_init(struct device_node *node,
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const struct clk_corediv_soc_desc *soc_desc)
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{
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struct clk_init_data init;
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struct clk_corediv *corediv;
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struct clk **clks;
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void __iomem *base;
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const char *parent_name;
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const char *clk_name;
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int i;
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base = of_iomap(node, 0);
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if (WARN_ON(!base))
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return;
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parent_name = of_clk_get_parent_name(node, 0);
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clk_data.clk_num = soc_desc->ndescs;
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/* clks holds the clock array */
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clks = kcalloc(clk_data.clk_num, sizeof(struct clk *),
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GFP_KERNEL);
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if (WARN_ON(!clks))
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goto err_unmap;
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/* corediv holds the clock specific array */
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corediv = kcalloc(clk_data.clk_num, sizeof(struct clk_corediv),
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GFP_KERNEL);
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if (WARN_ON(!corediv))
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goto err_free_clks;
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spin_lock_init(&corediv->lock);
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for (i = 0; i < clk_data.clk_num; i++) {
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of_property_read_string_index(node, "clock-output-names",
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i, &clk_name);
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init.num_parents = 1;
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init.parent_names = &parent_name;
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init.name = clk_name;
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init.ops = &soc_desc->ops;
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init.flags = 0;
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corediv[i].soc_desc = soc_desc;
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corediv[i].desc = soc_desc->descs + i;
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corediv[i].reg = base;
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corediv[i].hw.init = &init;
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clks[i] = clk_register(NULL, &corediv[i].hw);
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WARN_ON(IS_ERR(clks[i]));
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}
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clk_data.clks = clks;
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of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data);
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return;
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err_free_clks:
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kfree(clks);
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err_unmap:
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iounmap(base);
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}
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static void __init armada370_corediv_clk_init(struct device_node *node)
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{
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return mvebu_corediv_clk_init(node, &armada370_corediv_soc);
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}
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CLK_OF_DECLARE(armada370_corediv_clk, "marvell,armada-370-corediv-clock",
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armada370_corediv_clk_init);
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static void __init armada375_corediv_clk_init(struct device_node *node)
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{
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return mvebu_corediv_clk_init(node, &armada375_corediv_soc);
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}
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CLK_OF_DECLARE(armada375_corediv_clk, "marvell,armada-375-corediv-clock",
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armada375_corediv_clk_init);
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static void __init armada380_corediv_clk_init(struct device_node *node)
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{
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return mvebu_corediv_clk_init(node, &armada380_corediv_soc);
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}
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CLK_OF_DECLARE(armada380_corediv_clk, "marvell,armada-380-corediv-clock",
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armada380_corediv_clk_init);
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