294 lines
7.4 KiB
C
294 lines
7.4 KiB
C
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/*
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* Copyright (C) 2013 Emilio López <emilio@elopez.com.ar>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Adjustable factor-based clock implementation
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*/
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include "clk-factors.h"
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/*
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* DOC: basic adjustable factor-based clock
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*
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* Traits of this clock:
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* prepare - clk_prepare only ensures that parents are prepared
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* enable - clk_enable only ensures that parents are enabled
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* rate - rate is adjustable.
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* clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1)
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* parent - fixed parent. No clk_set_parent support
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*/
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#define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
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#define FACTORS_MAX_PARENTS 5
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#define SETMASK(len, pos) (((1U << (len)) - 1) << (pos))
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#define CLRMASK(len, pos) (~(SETMASK(len, pos)))
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#define FACTOR_GET(bit, len, reg) (((reg) & SETMASK(len, bit)) >> (bit))
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#define FACTOR_SET(bit, len, reg, val) \
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(((reg) & CLRMASK(len, bit)) | (val << (bit)))
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static unsigned long clk_factors_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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u8 n = 1, k = 0, p = 0, m = 0;
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u32 reg;
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unsigned long rate;
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struct clk_factors *factors = to_clk_factors(hw);
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const struct clk_factors_config *config = factors->config;
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/* Fetch the register value */
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reg = readl(factors->reg);
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/* Get each individual factor if applicable */
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if (config->nwidth != SUNXI_FACTORS_NOT_APPLICABLE)
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n = FACTOR_GET(config->nshift, config->nwidth, reg);
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if (config->kwidth != SUNXI_FACTORS_NOT_APPLICABLE)
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k = FACTOR_GET(config->kshift, config->kwidth, reg);
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if (config->mwidth != SUNXI_FACTORS_NOT_APPLICABLE)
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m = FACTOR_GET(config->mshift, config->mwidth, reg);
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if (config->pwidth != SUNXI_FACTORS_NOT_APPLICABLE)
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p = FACTOR_GET(config->pshift, config->pwidth, reg);
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if (factors->recalc) {
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struct factors_request factors_req = {
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.parent_rate = parent_rate,
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.n = n,
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.k = k,
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.m = m,
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.p = p,
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};
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/* get mux details from mux clk structure */
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if (factors->mux)
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factors_req.parent_index =
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(reg >> factors->mux->shift) &
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factors->mux->mask;
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factors->recalc(&factors_req);
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return factors_req.rate;
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}
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/* Calculate the rate */
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rate = (parent_rate * (n + config->n_start) * (k + 1) >> p) / (m + 1);
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return rate;
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}
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static int clk_factors_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_factors *factors = to_clk_factors(hw);
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struct clk_hw *parent, *best_parent = NULL;
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int i, num_parents;
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unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
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/* find the parent that can help provide the fastest rate <= rate */
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num_parents = clk_hw_get_num_parents(hw);
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for (i = 0; i < num_parents; i++) {
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struct factors_request factors_req = {
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.rate = req->rate,
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.parent_index = i,
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};
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parent = clk_hw_get_parent_by_index(hw, i);
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if (!parent)
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continue;
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
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parent_rate = clk_hw_round_rate(parent, req->rate);
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else
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parent_rate = clk_hw_get_rate(parent);
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factors_req.parent_rate = parent_rate;
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factors->get_factors(&factors_req);
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child_rate = factors_req.rate;
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if (child_rate <= req->rate && child_rate > best_child_rate) {
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best_parent = parent;
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best = parent_rate;
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best_child_rate = child_rate;
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}
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}
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if (!best_parent)
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return -EINVAL;
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req->best_parent_hw = best_parent;
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req->best_parent_rate = best;
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req->rate = best_child_rate;
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return 0;
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}
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static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct factors_request req = {
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.rate = rate,
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.parent_rate = parent_rate,
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};
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u32 reg;
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struct clk_factors *factors = to_clk_factors(hw);
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const struct clk_factors_config *config = factors->config;
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unsigned long flags = 0;
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factors->get_factors(&req);
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if (factors->lock)
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spin_lock_irqsave(factors->lock, flags);
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/* Fetch the register value */
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reg = readl(factors->reg);
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/* Set up the new factors - macros do not do anything if width is 0 */
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reg = FACTOR_SET(config->nshift, config->nwidth, reg, req.n);
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reg = FACTOR_SET(config->kshift, config->kwidth, reg, req.k);
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reg = FACTOR_SET(config->mshift, config->mwidth, reg, req.m);
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reg = FACTOR_SET(config->pshift, config->pwidth, reg, req.p);
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/* Apply them now */
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writel(reg, factors->reg);
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/* delay 500us so pll stabilizes */
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__delay((rate >> 20) * 500 / 2);
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if (factors->lock)
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spin_unlock_irqrestore(factors->lock, flags);
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return 0;
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}
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static const struct clk_ops clk_factors_ops = {
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.determine_rate = clk_factors_determine_rate,
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.recalc_rate = clk_factors_recalc_rate,
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.set_rate = clk_factors_set_rate,
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};
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struct clk *sunxi_factors_register(struct device_node *node,
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const struct factors_data *data,
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spinlock_t *lock,
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void __iomem *reg)
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{
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struct clk *clk;
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struct clk_factors *factors;
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struct clk_gate *gate = NULL;
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struct clk_mux *mux = NULL;
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struct clk_hw *gate_hw = NULL;
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struct clk_hw *mux_hw = NULL;
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const char *clk_name = node->name;
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const char *parents[FACTORS_MAX_PARENTS];
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int ret, i = 0;
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/* if we have a mux, we will have >1 parents */
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i = of_clk_parent_fill(node, parents, FACTORS_MAX_PARENTS);
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/*
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* some factor clocks, such as pll5 and pll6, may have multiple
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* outputs, and have their name designated in factors_data
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*/
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if (data->name)
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clk_name = data->name;
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else
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of_property_read_string(node, "clock-output-names", &clk_name);
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factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
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if (!factors)
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goto err_factors;
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/* set up factors properties */
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factors->reg = reg;
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factors->config = data->table;
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factors->get_factors = data->getter;
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factors->recalc = data->recalc;
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factors->lock = lock;
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/* Add a gate if this factor clock can be gated */
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if (data->enable) {
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gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
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if (!gate)
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goto err_gate;
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factors->gate = gate;
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/* set up gate properties */
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gate->reg = reg;
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gate->bit_idx = data->enable;
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gate->lock = factors->lock;
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gate_hw = &gate->hw;
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}
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/* Add a mux if this factor clock can be muxed */
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if (data->mux) {
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mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
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if (!mux)
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goto err_mux;
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factors->mux = mux;
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/* set up gate properties */
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mux->reg = reg;
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mux->shift = data->mux;
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mux->mask = data->muxmask;
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mux->lock = factors->lock;
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mux_hw = &mux->hw;
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}
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clk = clk_register_composite(NULL, clk_name,
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parents, i,
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mux_hw, &clk_mux_ops,
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&factors->hw, &clk_factors_ops,
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gate_hw, &clk_gate_ops, 0);
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if (IS_ERR(clk))
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goto err_register;
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ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
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if (ret)
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goto err_provider;
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return clk;
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err_provider:
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/* TODO: The composite clock stuff will leak a bit here. */
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clk_unregister(clk);
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err_register:
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kfree(mux);
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err_mux:
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kfree(gate);
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err_gate:
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kfree(factors);
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err_factors:
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return NULL;
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}
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void sunxi_factors_unregister(struct device_node *node, struct clk *clk)
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{
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struct clk_hw *hw = __clk_get_hw(clk);
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struct clk_factors *factors;
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const char *name;
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if (!hw)
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return;
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factors = to_clk_factors(hw);
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name = clk_hw_get_name(hw);
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of_clk_del_provider(node);
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/* TODO: The composite clock stuff will leak a bit here. */
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clk_unregister(clk);
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kfree(factors->mux);
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kfree(factors->gate);
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kfree(factors);
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}
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