159 lines
7.9 KiB
C
159 lines
7.9 KiB
C
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/*
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* Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include "clk.h"
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#include "clk-id.h"
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struct tegra_shared_clk {
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char *name;
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char *client;
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union {
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const char **parents;
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const char *parent;
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} p;
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int num_parents;
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enum shared_bus_users_mode mode;
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int flags;
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int clk_id;
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};
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#define SHARED_CLK(_name, _parent, _mode, _flags, _client, _id)\
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{\
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.name = _name,\
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.p.parent = _parent,\
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.num_parents = 1,\
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.mode = _mode, \
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.flags = _flags, \
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.client = _client,\
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.clk_id = _id,\
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}
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#define SHARED_LIMIT(_name, _parent, _mode, _flags, _client, _id)\
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{\
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.name = _name,\
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.p.parent = _parent,\
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.num_parents = 1,\
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.mode = _mode, \
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.flags = _flags | TEGRA_SHARED_BUS_RATE_LIMIT, \
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.client = _client,\
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.clk_id = _id,\
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}
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static struct tegra_shared_clk shared_clks[] = {
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SHARED_LIMIT("cap.c2bus", "c2bus", SHARED_CEILING, 0, NULL, tegra_clk_cap_c2bus),
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SHARED_LIMIT("cap.throttle.c2bus", "c2bus", SHARED_CEILING, 0, NULL, tegra_clk_cap_throttle_c2bus),
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SHARED_LIMIT("floor.c2bus", "c2bus", 0, 0, NULL, tegra_clk_floor_c2bus),
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SHARED_CLK("override.c2bus", "c2bus", SHARED_OVERRIDE, 0, NULL, tegra_clk_override_c2bus),
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SHARED_LIMIT("edp.c2bus", "c2bus", SHARED_CEILING, 0, NULL, tegra_clk_edp_c2bus),
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SHARED_LIMIT("battery.c2bus", "c2bus", SHARED_CEILING, 0, NULL, tegra_clk_battery_c2bus),
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SHARED_LIMIT("cap.profile.c2bus", "c2bus", SHARED_CEILING, 0, NULL, tegra_clk_cap_profile_c2bus),
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SHARED_LIMIT("cap.c3bus", "c3bus", SHARED_CEILING, 0, NULL, tegra_clk_cap_c3bus),
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SHARED_LIMIT("cap.throttle.c3bus", "c3bus", SHARED_CEILING, 0, NULL, tegra_clk_cap_throttle_c3bus),
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SHARED_CLK("override.c3bus", "c3bus", SHARED_OVERRIDE, 0, NULL, tegra_clk_override_c3bus),
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SHARED_LIMIT("floor.c3bus", "c3bus", 0, 0, NULL, tegra_clk_floor_c3bus),
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SHARED_LIMIT("cap.sclk", "sbus", SHARED_CEILING, 0, NULL, tegra_clk_cap_sclk),
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SHARED_LIMIT("cap.throttle.sclk", "sbus", SHARED_CEILING, 0, NULL, tegra_clk_cap_throttle_sclk),
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SHARED_LIMIT("floor.sclk", "sbus", 0, 0, NULL, tegra_clk_floor_sclk),
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SHARED_CLK("override.sclk", "sbus", SHARED_OVERRIDE, 0, NULL, tegra_clk_override_sclk),
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SHARED_CLK("avp.sclk", "sbus", 0, 0, NULL, tegra_clk_avp_sclk),
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SHARED_CLK("bsea.sclk", "sbus", 0, 0, NULL, tegra_clk_bsea_sclk),
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SHARED_CLK("usbd.sclk", "ahb.sclk", 0, 0, NULL, tegra_clk_usbd_sclk),
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SHARED_CLK("usb1.sclk", "ahb.sclk", 0, 0, NULL, tegra_clk_usb1_sclk),
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SHARED_CLK("usb2.sclk", "ahb.sclk", 0, 0, NULL, tegra_clk_usb2_sclk),
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SHARED_CLK("usb3.sclk", "ahb.sclk", 0, 0, NULL, tegra_clk_usb3_sclk),
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SHARED_CLK("wake.sclk", "sbus", 0, 0, NULL, tegra_clk_wake_sclk),
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SHARED_CLK("sbc1.sclk", "apb.sclk", 0, 0, NULL, tegra_clk_sbc1_sclk),
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SHARED_CLK("sbc2.sclk", "apb.sclk", 0, 0, NULL, tegra_clk_sbc2_sclk),
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SHARED_CLK("sbc3.sclk", "apb.sclk", 0, 0, NULL, tegra_clk_sbc3_sclk),
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SHARED_CLK("sbc4.sclk", "apb.sclk", 0, 0, NULL, tegra_clk_sbc4_sclk),
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SHARED_CLK("sbc5.sclk", "apb.sclk", 0, 0, NULL, tegra_clk_sbc5_sclk),
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SHARED_CLK("sbc6.sclk", "apb.sclk", 0, 0, NULL, tegra_clk_sbc6_sclk),
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SHARED_CLK("mon.avp", "sbus", 0, 0, NULL, tegra_clk_mon_avp),
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SHARED_LIMIT("cap.vcore.c2bus", "c2bus", SHARED_CEILING, 0, NULL, tegra_clk_cap_vcore_c2bus),
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SHARED_LIMIT("cap.vcore.c3bus", "c3bus", SHARED_CEILING, 0, NULL, tegra_clk_cap_vcore_c3bus),
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SHARED_CLK("camera.sclk", "sbus", 0, 0, NULL, tegra_clk_camera_sclk),
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SHARED_LIMIT("cap.vcore.sclk", "sbus", SHARED_CEILING, 0, NULL, tegra_clk_cap_vcore_sclk),
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SHARED_CLK("qspi.sclk", "apb.sclk", 0, 0, NULL, tegra_clk_qspi_sclk),
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SHARED_CLK("boot.apb.sclk", "apb.sclk", 0, 0, NULL, tegra_clk_boot_apb_sclk),
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SHARED_CLK("gm20b.gbus", "gbus", 0, 0, NULL, tegra_clk_gm20b_gbus),
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SHARED_LIMIT("cap.gbus", "gbus", SHARED_CEILING, 0, NULL, tegra_clk_cap_gbus),
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SHARED_LIMIT("edp.gbus", "gbus", SHARED_CEILING, 0, NULL, tegra_clk_edp_gbus),
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SHARED_LIMIT("cap.vgpu.gbus", "gbus", SHARED_CEILING, 0, NULL, tegra_clk_cap_vgpu_gbus),
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SHARED_LIMIT("cap.throttle_gbus", "gbus", SHARED_CEILING, 0, NULL, tegra_clk_cap_throttle_gbus),
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SHARED_LIMIT("cap.profile_gbus", "gbus", SHARED_CEILING, 0, NULL, tegra_clk_cap_profile_gbus),
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SHARED_CLK("override.gbus", "gbus", SHARED_OVERRIDE, 0, NULL, tegra_clk_override_gbus),
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SHARED_LIMIT("floor.gbus", "gbus", 0, 0, NULL, tegra_clk_floor_gbus),
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SHARED_LIMIT("floor.profile_gbus", "gbus", 0, 0, NULL, tegra_clk_floor_profile_gbus),
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SHARED_CLK("nv.host1x", "host1x_master", 0, 0, NULL, tegra_clk_nv_host1x),
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SHARED_CLK("vi.host1x", "host1x_master", 0, 0, NULL, tegra_clk_vi_host1x),
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SHARED_CLK("vii2c.host1x", "host1x_master", 0, 0, NULL, tegra_clk_vii2c_host1x),
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SHARED_LIMIT("cap.host1x", "host1x_master", SHARED_CEILING, 0, NULL, tegra_clk_cap_host1x),
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SHARED_LIMIT("cap.vcore.host1x", "host1x_master", SHARED_CEILING, 0, NULL, tegra_clk_cap_vcore_host1x),
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SHARED_LIMIT("floor.host1x", "host1x_master", 0, 0, NULL, tegra_clk_floor_host1x),
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SHARED_CLK("override.host1x", "host1x_master", SHARED_OVERRIDE, 0, NULL, tegra_clk_override_host1x),
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SHARED_CLK("cpu.mselect", "mselect_master", 0, 0, NULL, tegra_clk_cpu_mselect),
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SHARED_CLK("pcie.mselect", "mselect_master", 0, 0, NULL, tegra_clk_pcie_mselect),
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SHARED_LIMIT("cap.vcore.mselect", "mselect_master", SHARED_CEILING, 0, NULL, tegra_clk_cap_vcore_mselect),
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SHARED_CLK("override.mselect", "mselect_master", SHARED_OVERRIDE, 0, NULL, tegra_clk_override_mselect),
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SHARED_CLK("adma.ape", "ape_master", 0, 0, NULL, tegra_clk_adma_ape),
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SHARED_CLK("adsp.ape", "ape_master", 0, 0, NULL, tegra_clk_adsp_ape),
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SHARED_CLK("xbar.ape", "ape_master", 0, 0, NULL, tegra_clk_xbar_ape),
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SHARED_LIMIT("cap.vcore.ape", "ape_master", SHARED_CEILING, 0, NULL, tegra_clk_cap_vcore_ape),
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SHARED_LIMIT("override.ape", "ape_master", SHARED_OVERRIDE, 0, NULL, tegra_clk_override_ape),
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SHARED_CLK("adsp.cpu.abus", "abus", 0, 0, "aclk", tegra_clk_adsp_cpu_abus),
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SHARED_LIMIT("cap.vcore.abus", "abus", SHARED_CEILING, 0, NULL, tegra_clk_cap_vcore_abus),
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SHARED_CLK("override.abus", "abus", SHARED_OVERRIDE, 0, NULL, tegra_clk_override_abus),
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SHARED_LIMIT("cap.vcore.cbus", "cbus", SHARED_CEILING, 0, NULL, tegra_clk_cap_vcore_cbus),
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SHARED_CLK("override.cbus", "cbus", SHARED_OVERRIDE, 0, NULL, tegra_clk_override_cbus),
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SHARED_CLK("sdmmc4.sclk", "ahb.sclk", 0, 0, NULL, tegra_clk_sdmmc4_ahb_sclk),
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SHARED_LIMIT("vic.floor.cbus", "c2bus", 0, 0, NULL, tegra_clk_vic_floor_cbus),
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SHARED_CLK("override.emc", "emc_master", SHARED_OVERRIDE, 0, NULL, tegra_clk_override_emc),
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SHARED_CLK("bwmgr.emc", "emc_master", 0, 0, NULL, tegra_clk_bwmgr_emc),
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SHARED_CLK("vcm.sclk", "sbus", 0, 0, NULL, tegra_clk_vcm_sclk),
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SHARED_CLK("vcm.ahb.sclk", "ahb.sclk", 0, 0, NULL, tegra_clk_vcm_ahb_sclk),
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SHARED_CLK("vcm.apb.sclk", "apb.sclk", 0, 0, NULL, tegra_clk_vcm_apb_sclk),
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SHARED_CLK("wifi.sclk", "apb.sclk", 0, 0, NULL, tegra_clk_wifi_sclk),
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};
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void __init tegra_shared_clk_init(struct tegra_clk *tegra_clks)
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{
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int i;
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const char **parents;
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struct tegra_shared_clk *data;
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struct clk *clk;
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struct clk **dt_clk;
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for (i = 0; i < ARRAY_SIZE(shared_clks); i++) {
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data = &shared_clks[i];
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if (data->num_parents == 1)
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parents = &data->p.parent;
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else
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parents = data->p.parents;
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dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
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if (!dt_clk)
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continue;
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clk = tegra_clk_register_shared(data->name, parents,
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data->num_parents, data->flags, data->mode,
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data->client);
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*dt_clk = clk;
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}
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}
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