228 lines
6.2 KiB
C
228 lines
6.2 KiB
C
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/*
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* OMAP4-specific DPLL control functions
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*
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* Copyright (C) 2011 Texas Instruments, Inc.
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* Rajendra Nayak
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <linux/clk/ti.h>
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#include "clock.h"
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/*
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* Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
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* can supported when using the DPLL low-power mode. Frequencies are
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* defined in OMAP4430/60 Public TRM section 3.6.3.3.2 "Enable Control,
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* Status, and Low-Power Operation Mode".
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*/
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#define OMAP4_DPLL_LP_FINT_MAX 1000000
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#define OMAP4_DPLL_LP_FOUT_MAX 100000000
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/*
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* Bitfield declarations
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*/
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#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BIT(8)
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#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BIT(10)
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#define OMAP4430_DPLL_REGM4XEN_MASK BIT(11)
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/* Static rate multiplier for OMAP4 REGM4XEN clocks */
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#define OMAP4430_REGM4XEN_MULT 4
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static void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
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{
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u32 v;
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u32 mask;
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if (!clk || !clk->clksel_reg)
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return;
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mask = clk->flags & CLOCK_CLKOUTX2 ?
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OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
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OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
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v = ti_clk_ll_ops->clk_readl(clk->clksel_reg);
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/* Clear the bit to allow gatectrl */
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v &= ~mask;
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ti_clk_ll_ops->clk_writel(v, clk->clksel_reg);
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}
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static void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
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{
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u32 v;
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u32 mask;
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if (!clk || !clk->clksel_reg)
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return;
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mask = clk->flags & CLOCK_CLKOUTX2 ?
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OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
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OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
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v = ti_clk_ll_ops->clk_readl(clk->clksel_reg);
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/* Set the bit to deny gatectrl */
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v |= mask;
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ti_clk_ll_ops->clk_writel(v, clk->clksel_reg);
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}
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const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
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.allow_idle = omap4_dpllmx_allow_gatectrl,
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.deny_idle = omap4_dpllmx_deny_gatectrl,
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};
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/**
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* omap4_dpll_lpmode_recalc - compute DPLL low-power setting
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* @dd: pointer to the dpll data structure
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*
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* Calculates if low-power mode can be enabled based upon the last
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* multiplier and divider values calculated. If low-power mode can be
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* enabled, then the bit to enable low-power mode is stored in the
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* last_rounded_lpmode variable. This implementation is based upon the
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* criteria for enabling low-power mode as described in the OMAP4430/60
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* Public TRM section 3.6.3.3.2 "Enable Control, Status, and Low-Power
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* Operation Mode".
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*/
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static void omap4_dpll_lpmode_recalc(struct dpll_data *dd)
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{
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long fint, fout;
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fint = clk_hw_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1);
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fout = fint * dd->last_rounded_m;
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if ((fint < OMAP4_DPLL_LP_FINT_MAX) && (fout < OMAP4_DPLL_LP_FOUT_MAX))
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dd->last_rounded_lpmode = 1;
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else
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dd->last_rounded_lpmode = 0;
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}
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/**
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* omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
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* @clk: struct clk * of the DPLL to compute the rate for
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*
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* Compute the output rate for the OMAP4 DPLL represented by @clk.
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* Takes the REGM4XEN bit into consideration, which is needed for the
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* OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
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* upon success, or 0 upon error.
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*/
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unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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u32 v;
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unsigned long rate;
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struct dpll_data *dd;
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if (!clk || !clk->dpll_data)
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return 0;
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dd = clk->dpll_data;
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rate = omap2_get_dpll_rate(clk);
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/* regm4xen adds a multiplier of 4 to DPLL calculations */
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v = ti_clk_ll_ops->clk_readl(dd->control_reg);
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if (v & OMAP4430_DPLL_REGM4XEN_MASK)
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rate *= OMAP4430_REGM4XEN_MULT;
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return rate;
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}
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/**
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* omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
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* @clk: struct clk * of the DPLL to round a rate for
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* @target_rate: the desired rate of the DPLL
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*
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* Compute the rate that would be programmed into the DPLL hardware
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* for @clk if set_rate() were to be provided with the rate
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* @target_rate. Takes the REGM4XEN bit into consideration, which is
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* needed for the OMAP4 ABE DPLL. Returns the rounded rate (before
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* M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
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* ~0 if an error occurred in omap2_dpll_round_rate().
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*/
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long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
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unsigned long target_rate,
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unsigned long *parent_rate)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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struct dpll_data *dd;
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long r;
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if (!clk || !clk->dpll_data)
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return -EINVAL;
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dd = clk->dpll_data;
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dd->last_rounded_m4xen = 0;
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/*
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* First try to compute the DPLL configuration for
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* target rate without using the 4X multiplier.
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*/
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r = omap2_dpll_round_rate(hw, target_rate, NULL);
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if (r != ~0)
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goto out;
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/*
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* If we did not find a valid DPLL configuration, try again, but
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* this time see if using the 4X multiplier can help. Enabling the
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* 4X multiplier is equivalent to dividing the target rate by 4.
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*/
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r = omap2_dpll_round_rate(hw, target_rate / OMAP4430_REGM4XEN_MULT,
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NULL);
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if (r == ~0)
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return r;
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dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
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dd->last_rounded_m4xen = 1;
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out:
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omap4_dpll_lpmode_recalc(dd);
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return dd->last_rounded_rate;
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}
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/**
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* omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL
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* @hw: pointer to the clock to determine rate for
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* @req: target rate request
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*
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* Determines which DPLL mode to use for reaching a desired rate.
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* Checks whether the DPLL shall be in bypass or locked mode, and if
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* locked, calculates the M,N values for the DPLL via round-rate.
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* Returns 0 on success and a negative error value otherwise.
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*/
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int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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struct dpll_data *dd;
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if (!req->rate)
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return -EINVAL;
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dd = clk->dpll_data;
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if (!dd)
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return -EINVAL;
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if (clk_hw_get_rate(dd->clk_bypass) == req->rate &&
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(dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
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req->best_parent_hw = dd->clk_bypass;
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} else {
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req->rate = omap4_dpll_regm4xen_round_rate(hw, req->rate,
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&req->best_parent_rate);
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req->best_parent_hw = dd->clk_ref;
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}
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req->best_parent_rate = req->rate;
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return 0;
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}
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