212 lines
4.9 KiB
C
212 lines
4.9 KiB
C
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/*
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* Rockchip timer support
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*
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* Copyright (C) Daniel Lezcano <daniel.lezcano@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#define TIMER_NAME "rk_timer"
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#define TIMER_LOAD_COUNT0 0x00
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#define TIMER_LOAD_COUNT1 0x04
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#define TIMER_CONTROL_REG3288 0x10
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#define TIMER_CONTROL_REG3399 0x1c
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#define TIMER_INT_STATUS 0x18
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#define TIMER_DISABLE 0x0
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#define TIMER_ENABLE 0x1
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#define TIMER_MODE_FREE_RUNNING (0 << 1)
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#define TIMER_MODE_USER_DEFINED_COUNT (1 << 1)
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#define TIMER_INT_UNMASK (1 << 2)
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struct bc_timer {
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struct clock_event_device ce;
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void __iomem *base;
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void __iomem *ctrl;
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u32 freq;
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};
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static struct bc_timer bc_timer;
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static inline struct bc_timer *rk_timer(struct clock_event_device *ce)
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{
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return container_of(ce, struct bc_timer, ce);
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}
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static inline void __iomem *rk_base(struct clock_event_device *ce)
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{
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return rk_timer(ce)->base;
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}
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static inline void __iomem *rk_ctrl(struct clock_event_device *ce)
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{
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return rk_timer(ce)->ctrl;
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}
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static inline void rk_timer_disable(struct clock_event_device *ce)
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{
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writel_relaxed(TIMER_DISABLE, rk_ctrl(ce));
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}
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static inline void rk_timer_enable(struct clock_event_device *ce, u32 flags)
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{
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writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags,
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rk_ctrl(ce));
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}
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static void rk_timer_update_counter(unsigned long cycles,
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struct clock_event_device *ce)
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{
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writel_relaxed(cycles, rk_base(ce) + TIMER_LOAD_COUNT0);
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writel_relaxed(0, rk_base(ce) + TIMER_LOAD_COUNT1);
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}
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static void rk_timer_interrupt_clear(struct clock_event_device *ce)
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{
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writel_relaxed(1, rk_base(ce) + TIMER_INT_STATUS);
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}
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static inline int rk_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *ce)
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{
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rk_timer_disable(ce);
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rk_timer_update_counter(cycles, ce);
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rk_timer_enable(ce, TIMER_MODE_USER_DEFINED_COUNT);
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return 0;
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}
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static int rk_timer_shutdown(struct clock_event_device *ce)
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{
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rk_timer_disable(ce);
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return 0;
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}
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static int rk_timer_set_periodic(struct clock_event_device *ce)
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{
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rk_timer_disable(ce);
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rk_timer_update_counter(rk_timer(ce)->freq / HZ - 1, ce);
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rk_timer_enable(ce, TIMER_MODE_FREE_RUNNING);
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return 0;
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}
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static irqreturn_t rk_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *ce = dev_id;
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rk_timer_interrupt_clear(ce);
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if (clockevent_state_oneshot(ce))
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rk_timer_disable(ce);
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ce->event_handler(ce);
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return IRQ_HANDLED;
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}
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static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
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{
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struct clock_event_device *ce = &bc_timer.ce;
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struct clk *timer_clk;
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struct clk *pclk;
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int ret = -EINVAL, irq;
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bc_timer.base = of_iomap(np, 0);
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if (!bc_timer.base) {
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pr_err("Failed to get base address for '%s'\n", TIMER_NAME);
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return -ENXIO;
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}
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bc_timer.ctrl = bc_timer.base + ctrl_reg;
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pclk = of_clk_get_by_name(np, "pclk");
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if (IS_ERR(pclk)) {
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ret = PTR_ERR(pclk);
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pr_err("Failed to get pclk for '%s'\n", TIMER_NAME);
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goto out_unmap;
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}
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ret = clk_prepare_enable(pclk);
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if (ret) {
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pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME);
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goto out_unmap;
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}
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timer_clk = of_clk_get_by_name(np, "timer");
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if (IS_ERR(timer_clk)) {
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ret = PTR_ERR(timer_clk);
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pr_err("Failed to get timer clock for '%s'\n", TIMER_NAME);
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goto out_timer_clk;
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}
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ret = clk_prepare_enable(timer_clk);
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if (ret) {
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pr_err("Failed to enable timer clock\n");
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goto out_timer_clk;
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}
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bc_timer.freq = clk_get_rate(timer_clk);
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irq = irq_of_parse_and_map(np, 0);
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if (!irq) {
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ret = -EINVAL;
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pr_err("Failed to map interrupts for '%s'\n", TIMER_NAME);
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goto out_irq;
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}
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ce->name = TIMER_NAME;
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ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_DYNIRQ;
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ce->set_next_event = rk_timer_set_next_event;
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ce->set_state_shutdown = rk_timer_shutdown;
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ce->set_state_periodic = rk_timer_set_periodic;
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ce->irq = irq;
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ce->cpumask = cpu_possible_mask;
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ce->rating = 250;
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rk_timer_interrupt_clear(ce);
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rk_timer_disable(ce);
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ret = request_irq(irq, rk_timer_interrupt, IRQF_TIMER, TIMER_NAME, ce);
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if (ret) {
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pr_err("Failed to initialize '%s': %d\n", TIMER_NAME, ret);
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goto out_irq;
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}
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clockevents_config_and_register(ce, bc_timer.freq, 1, UINT_MAX);
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return 0;
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out_irq:
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clk_disable_unprepare(timer_clk);
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out_timer_clk:
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clk_disable_unprepare(pclk);
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out_unmap:
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iounmap(bc_timer.base);
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return ret;
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}
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static int __init rk3288_timer_init(struct device_node *np)
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{
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return rk_timer_init(np, TIMER_CONTROL_REG3288);
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}
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static int __init rk3399_timer_init(struct device_node *np)
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{
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return rk_timer_init(np, TIMER_CONTROL_REG3399);
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}
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CLOCKSOURCE_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer",
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rk3288_timer_init);
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CLOCKSOURCE_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer",
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rk3399_timer_init);
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