101 lines
3.0 KiB
C
101 lines
3.0 KiB
C
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/*
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* Copyright (c) 2016, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/interrupt.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/cpu.h>
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#include <soc/nps/common.h>
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#define NPS_MSU_TICK_LOW 0xC8
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#define NPS_CLUSTER_OFFSET 8
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#define NPS_CLUSTER_NUM 16
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/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
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static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
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static unsigned long nps_timer_rate;
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static cycle_t nps_clksrc_read(struct clocksource *clksrc)
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{
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int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
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return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
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}
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static int __init nps_setup_clocksource(struct device_node *node,
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struct clk *clk)
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{
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int ret, cluster;
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for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
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nps_msu_reg_low_addr[cluster] =
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nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
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NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("Couldn't enable parent clock\n");
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return ret;
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}
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nps_timer_rate = clk_get_rate(clk);
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ret = clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick",
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nps_timer_rate, 301, 32, nps_clksrc_read);
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if (ret) {
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pr_err("Couldn't register clock source.\n");
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clk_disable_unprepare(clk);
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}
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return ret;
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}
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static int __init nps_timer_init(struct device_node *node)
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{
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struct clk *clk;
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk)) {
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pr_err("Can't get timer clock.\n");
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return PTR_ERR(clk);
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}
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return nps_setup_clocksource(node, clk);
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}
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CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
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nps_timer_init);
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