352 lines
8.8 KiB
C
352 lines
8.8 KiB
C
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/*
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* Provide TDMA helper functions used by cipher and hash algorithm
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* implementations.
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*
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* Author: Boris Brezillon <boris.brezillon@free-electrons.com>
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* Author: Arnaud Ebalard <arno@natisbad.org>
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*
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* This work is based on an initial version written by
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* Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include "cesa.h"
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bool mv_cesa_req_dma_iter_next_transfer(struct mv_cesa_dma_iter *iter,
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struct mv_cesa_sg_dma_iter *sgiter,
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unsigned int len)
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{
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if (!sgiter->sg)
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return false;
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sgiter->op_offset += len;
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sgiter->offset += len;
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if (sgiter->offset == sg_dma_len(sgiter->sg)) {
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if (sg_is_last(sgiter->sg))
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return false;
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sgiter->offset = 0;
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sgiter->sg = sg_next(sgiter->sg);
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}
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if (sgiter->op_offset == iter->op_len)
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return false;
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return true;
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}
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void mv_cesa_dma_step(struct mv_cesa_req *dreq)
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{
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struct mv_cesa_engine *engine = dreq->engine;
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writel_relaxed(0, engine->regs + CESA_SA_CFG);
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mv_cesa_set_int_mask(engine, CESA_SA_INT_ACC0_IDMA_DONE);
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writel_relaxed(CESA_TDMA_DST_BURST_128B | CESA_TDMA_SRC_BURST_128B |
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CESA_TDMA_NO_BYTE_SWAP | CESA_TDMA_EN,
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engine->regs + CESA_TDMA_CONTROL);
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writel_relaxed(CESA_SA_CFG_ACT_CH0_IDMA | CESA_SA_CFG_MULTI_PKT |
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CESA_SA_CFG_CH0_W_IDMA | CESA_SA_CFG_PARA_DIS,
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engine->regs + CESA_SA_CFG);
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writel_relaxed(dreq->chain.first->cur_dma,
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engine->regs + CESA_TDMA_NEXT_ADDR);
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BUG_ON(readl(engine->regs + CESA_SA_CMD) &
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CESA_SA_CMD_EN_CESA_SA_ACCL0);
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writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
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}
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void mv_cesa_dma_cleanup(struct mv_cesa_req *dreq)
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{
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struct mv_cesa_tdma_desc *tdma;
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for (tdma = dreq->chain.first; tdma;) {
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struct mv_cesa_tdma_desc *old_tdma = tdma;
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u32 type = tdma->flags & CESA_TDMA_TYPE_MSK;
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if (type == CESA_TDMA_OP)
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dma_pool_free(cesa_dev->dma->op_pool, tdma->op,
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le32_to_cpu(tdma->src));
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else if (type == CESA_TDMA_IV)
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dma_pool_free(cesa_dev->dma->iv_pool, tdma->data,
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le32_to_cpu(tdma->dst));
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tdma = tdma->next;
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dma_pool_free(cesa_dev->dma->tdma_desc_pool, old_tdma,
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old_tdma->cur_dma);
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}
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dreq->chain.first = NULL;
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dreq->chain.last = NULL;
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}
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void mv_cesa_dma_prepare(struct mv_cesa_req *dreq,
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struct mv_cesa_engine *engine)
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{
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struct mv_cesa_tdma_desc *tdma;
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for (tdma = dreq->chain.first; tdma; tdma = tdma->next) {
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if (tdma->flags & CESA_TDMA_DST_IN_SRAM)
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tdma->dst = cpu_to_le32(tdma->dst + engine->sram_dma);
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if (tdma->flags & CESA_TDMA_SRC_IN_SRAM)
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tdma->src = cpu_to_le32(tdma->src + engine->sram_dma);
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if ((tdma->flags & CESA_TDMA_TYPE_MSK) == CESA_TDMA_OP)
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mv_cesa_adjust_op(engine, tdma->op);
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}
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}
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void mv_cesa_tdma_chain(struct mv_cesa_engine *engine,
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struct mv_cesa_req *dreq)
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{
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if (engine->chain.first == NULL && engine->chain.last == NULL) {
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engine->chain.first = dreq->chain.first;
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engine->chain.last = dreq->chain.last;
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} else {
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struct mv_cesa_tdma_desc *last;
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last = engine->chain.last;
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last->next = dreq->chain.first;
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engine->chain.last = dreq->chain.last;
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/*
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* Break the DMA chain if the CESA_TDMA_BREAK_CHAIN is set on
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* the last element of the current chain, or if the request
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* being queued needs the IV regs to be set before lauching
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* the request.
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*/
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if (!(last->flags & CESA_TDMA_BREAK_CHAIN) &&
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!(dreq->chain.first->flags & CESA_TDMA_SET_STATE))
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last->next_dma = dreq->chain.first->cur_dma;
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}
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}
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int mv_cesa_tdma_process(struct mv_cesa_engine *engine, u32 status)
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{
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struct crypto_async_request *req = NULL;
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struct mv_cesa_tdma_desc *tdma = NULL, *next = NULL;
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dma_addr_t tdma_cur;
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int res = 0;
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tdma_cur = readl(engine->regs + CESA_TDMA_CUR);
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for (tdma = engine->chain.first; tdma; tdma = next) {
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spin_lock_bh(&engine->lock);
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next = tdma->next;
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spin_unlock_bh(&engine->lock);
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if (tdma->flags & CESA_TDMA_END_OF_REQ) {
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struct crypto_async_request *backlog = NULL;
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struct mv_cesa_ctx *ctx;
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u32 current_status;
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spin_lock_bh(&engine->lock);
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/*
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* if req is NULL, this means we're processing the
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* request in engine->req.
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*/
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if (!req)
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req = engine->req;
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else
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req = mv_cesa_dequeue_req_locked(engine,
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&backlog);
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/* Re-chaining to the next request */
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engine->chain.first = tdma->next;
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tdma->next = NULL;
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/* If this is the last request, clear the chain */
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if (engine->chain.first == NULL)
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engine->chain.last = NULL;
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spin_unlock_bh(&engine->lock);
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ctx = crypto_tfm_ctx(req->tfm);
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current_status = (tdma->cur_dma == tdma_cur) ?
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status : CESA_SA_INT_ACC0_IDMA_DONE;
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res = ctx->ops->process(req, current_status);
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ctx->ops->complete(req);
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if (res == 0)
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mv_cesa_engine_enqueue_complete_request(engine,
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req);
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if (backlog)
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backlog->complete(backlog, -EINPROGRESS);
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}
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if (res || tdma->cur_dma == tdma_cur)
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break;
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}
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/* Save the last request in error to engine->req, so that the core
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* knows which request was fautly */
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if (res) {
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spin_lock_bh(&engine->lock);
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engine->req = req;
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spin_unlock_bh(&engine->lock);
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}
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return res;
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}
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static struct mv_cesa_tdma_desc *
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mv_cesa_dma_add_desc(struct mv_cesa_tdma_chain *chain, gfp_t flags)
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{
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struct mv_cesa_tdma_desc *new_tdma = NULL;
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dma_addr_t dma_handle;
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new_tdma = dma_pool_zalloc(cesa_dev->dma->tdma_desc_pool, flags,
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&dma_handle);
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if (!new_tdma)
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return ERR_PTR(-ENOMEM);
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new_tdma->cur_dma = dma_handle;
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if (chain->last) {
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chain->last->next_dma = cpu_to_le32(dma_handle);
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chain->last->next = new_tdma;
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} else {
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chain->first = new_tdma;
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}
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chain->last = new_tdma;
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return new_tdma;
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}
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int mv_cesa_dma_add_iv_op(struct mv_cesa_tdma_chain *chain, dma_addr_t src,
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u32 size, u32 flags, gfp_t gfp_flags)
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{
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struct mv_cesa_tdma_desc *tdma;
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u8 *iv;
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dma_addr_t dma_handle;
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tdma = mv_cesa_dma_add_desc(chain, gfp_flags);
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if (IS_ERR(tdma))
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return PTR_ERR(tdma);
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iv = dma_pool_alloc(cesa_dev->dma->iv_pool, gfp_flags, &dma_handle);
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if (!iv)
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return -ENOMEM;
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tdma->byte_cnt = cpu_to_le32(size | BIT(31));
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tdma->src = src;
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tdma->dst = cpu_to_le32(dma_handle);
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tdma->data = iv;
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flags &= (CESA_TDMA_DST_IN_SRAM | CESA_TDMA_SRC_IN_SRAM);
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tdma->flags = flags | CESA_TDMA_IV;
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return 0;
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}
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struct mv_cesa_op_ctx *mv_cesa_dma_add_op(struct mv_cesa_tdma_chain *chain,
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const struct mv_cesa_op_ctx *op_templ,
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bool skip_ctx,
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gfp_t flags)
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{
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struct mv_cesa_tdma_desc *tdma;
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struct mv_cesa_op_ctx *op;
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dma_addr_t dma_handle;
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unsigned int size;
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tdma = mv_cesa_dma_add_desc(chain, flags);
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if (IS_ERR(tdma))
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return ERR_CAST(tdma);
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op = dma_pool_alloc(cesa_dev->dma->op_pool, flags, &dma_handle);
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if (!op)
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return ERR_PTR(-ENOMEM);
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*op = *op_templ;
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size = skip_ctx ? sizeof(op->desc) : sizeof(*op);
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tdma = chain->last;
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tdma->op = op;
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tdma->byte_cnt = cpu_to_le32(size | BIT(31));
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tdma->src = cpu_to_le32(dma_handle);
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tdma->dst = CESA_SA_CFG_SRAM_OFFSET;
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tdma->flags = CESA_TDMA_DST_IN_SRAM | CESA_TDMA_OP;
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return op;
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}
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int mv_cesa_dma_add_data_transfer(struct mv_cesa_tdma_chain *chain,
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dma_addr_t dst, dma_addr_t src, u32 size,
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u32 flags, gfp_t gfp_flags)
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{
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struct mv_cesa_tdma_desc *tdma;
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tdma = mv_cesa_dma_add_desc(chain, gfp_flags);
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if (IS_ERR(tdma))
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return PTR_ERR(tdma);
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tdma->byte_cnt = cpu_to_le32(size | BIT(31));
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tdma->src = src;
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tdma->dst = dst;
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flags &= (CESA_TDMA_DST_IN_SRAM | CESA_TDMA_SRC_IN_SRAM);
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tdma->flags = flags | CESA_TDMA_DATA;
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return 0;
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}
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int mv_cesa_dma_add_dummy_launch(struct mv_cesa_tdma_chain *chain, gfp_t flags)
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{
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struct mv_cesa_tdma_desc *tdma;
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tdma = mv_cesa_dma_add_desc(chain, flags);
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if (IS_ERR(tdma))
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return PTR_ERR(tdma);
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return 0;
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}
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int mv_cesa_dma_add_dummy_end(struct mv_cesa_tdma_chain *chain, gfp_t flags)
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{
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struct mv_cesa_tdma_desc *tdma;
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tdma = mv_cesa_dma_add_desc(chain, flags);
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if (IS_ERR(tdma))
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return PTR_ERR(tdma);
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tdma->byte_cnt = cpu_to_le32(BIT(31));
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return 0;
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}
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int mv_cesa_dma_add_op_transfers(struct mv_cesa_tdma_chain *chain,
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struct mv_cesa_dma_iter *dma_iter,
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struct mv_cesa_sg_dma_iter *sgiter,
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gfp_t gfp_flags)
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{
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u32 flags = sgiter->dir == DMA_TO_DEVICE ?
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CESA_TDMA_DST_IN_SRAM : CESA_TDMA_SRC_IN_SRAM;
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unsigned int len;
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do {
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dma_addr_t dst, src;
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int ret;
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len = mv_cesa_req_dma_iter_transfer_len(dma_iter, sgiter);
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if (sgiter->dir == DMA_TO_DEVICE) {
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dst = CESA_SA_DATA_SRAM_OFFSET + sgiter->op_offset;
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src = sg_dma_address(sgiter->sg) + sgiter->offset;
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} else {
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dst = sg_dma_address(sgiter->sg) + sgiter->offset;
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src = CESA_SA_DATA_SRAM_OFFSET + sgiter->op_offset;
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}
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ret = mv_cesa_dma_add_data_transfer(chain, dst, src, len,
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flags, gfp_flags);
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if (ret)
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return ret;
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} while (mv_cesa_req_dma_iter_next_transfer(dma_iter, sgiter, len));
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return 0;
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}
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