409 lines
11 KiB
C
409 lines
11 KiB
C
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/*
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* GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
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*
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* Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
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* Copyright (C) 2016 Freescale Semiconductor Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/slab.h>
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#include <linux/irq.h>
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#include <linux/gpio/driver.h>
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#define MPC8XXX_GPIO_PINS 32
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#define GPIO_DIR 0x00
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#define GPIO_ODR 0x04
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#define GPIO_DAT 0x08
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#define GPIO_IER 0x0c
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#define GPIO_IMR 0x10
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#define GPIO_ICR 0x14
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#define GPIO_ICR2 0x18
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struct mpc8xxx_gpio_chip {
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struct gpio_chip gc;
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void __iomem *regs;
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raw_spinlock_t lock;
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int (*direction_output)(struct gpio_chip *chip,
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unsigned offset, int value);
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struct irq_domain *irq;
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unsigned int irqn;
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};
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/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
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* defined as output cannot be determined by reading GPDAT register,
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* so we use shadow data register instead. The status of input pins
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* is determined by reading GPDAT register.
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*/
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static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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u32 val;
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
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u32 out_mask, out_shadow;
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out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
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val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
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out_shadow = gc->bgpio_data & out_mask;
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return !!((val | out_shadow) & gc->pin2mask(gc, gpio));
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}
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static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
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unsigned int gpio, int val)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
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/* GPIO 28..31 are input only on MPC5121 */
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if (gpio >= 28)
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return -EINVAL;
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return mpc8xxx_gc->direction_output(gc, gpio, val);
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}
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static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
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unsigned int gpio, int val)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
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/* GPIO 0..3 are input only on MPC5125 */
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if (gpio <= 3)
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return -EINVAL;
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return mpc8xxx_gc->direction_output(gc, gpio, val);
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}
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static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
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if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
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return irq_create_mapping(mpc8xxx_gc->irq, offset);
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else
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return -ENXIO;
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}
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static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct gpio_chip *gc = &mpc8xxx_gc->gc;
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unsigned int mask;
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mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
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& gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
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if (mask)
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generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
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32 - ffs(mask)));
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if (chip->irq_eoi)
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chip->irq_eoi(&desc->irq_data);
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}
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static void mpc8xxx_irq_unmask(struct irq_data *d)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct gpio_chip *gc = &mpc8xxx_gc->gc;
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unsigned long flags;
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
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gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
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| gc->pin2mask(gc, irqd_to_hwirq(d)));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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static void mpc8xxx_irq_mask(struct irq_data *d)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct gpio_chip *gc = &mpc8xxx_gc->gc;
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unsigned long flags;
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
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gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
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& ~(gc->pin2mask(gc, irqd_to_hwirq(d))));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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static void mpc8xxx_irq_ack(struct irq_data *d)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct gpio_chip *gc = &mpc8xxx_gc->gc;
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gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
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gc->pin2mask(gc, irqd_to_hwirq(d)));
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}
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static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct gpio_chip *gc = &mpc8xxx_gc->gc;
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unsigned long flags;
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switch (flow_type) {
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case IRQ_TYPE_EDGE_FALLING:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
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gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
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| gc->pin2mask(gc, irqd_to_hwirq(d)));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
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gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
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& ~(gc->pin2mask(gc, irqd_to_hwirq(d))));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct gpio_chip *gc = &mpc8xxx_gc->gc;
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unsigned long gpio = irqd_to_hwirq(d);
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void __iomem *reg;
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unsigned int shift;
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unsigned long flags;
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if (gpio < 16) {
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reg = mpc8xxx_gc->regs + GPIO_ICR;
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shift = (15 - gpio) * 2;
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} else {
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reg = mpc8xxx_gc->regs + GPIO_ICR2;
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shift = (15 - (gpio % 16)) * 2;
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}
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switch (flow_type) {
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_LEVEL_LOW:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
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| (2 << shift));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_LEVEL_HIGH:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
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| (1 << shift));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static struct irq_chip mpc8xxx_irq_chip = {
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.name = "mpc8xxx-gpio",
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.irq_unmask = mpc8xxx_irq_unmask,
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.irq_mask = mpc8xxx_irq_mask,
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.irq_ack = mpc8xxx_irq_ack,
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/* this might get overwritten in mpc8xxx_probe() */
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.irq_set_type = mpc8xxx_irq_set_type,
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};
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static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_data(irq, h->host_data);
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irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
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return 0;
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}
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static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
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.map = mpc8xxx_gpio_irq_map,
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.xlate = irq_domain_xlate_twocell,
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};
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struct mpc8xxx_gpio_devtype {
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int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
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int (*gpio_get)(struct gpio_chip *, unsigned int);
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int (*irq_set_type)(struct irq_data *, unsigned int);
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};
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static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
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.gpio_dir_out = mpc5121_gpio_dir_out,
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.irq_set_type = mpc512x_irq_set_type,
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};
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static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
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.gpio_dir_out = mpc5125_gpio_dir_out,
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.irq_set_type = mpc512x_irq_set_type,
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};
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static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
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.gpio_get = mpc8572_gpio_get,
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};
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static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
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.irq_set_type = mpc8xxx_irq_set_type,
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};
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static const struct of_device_id mpc8xxx_gpio_ids[] = {
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{ .compatible = "fsl,mpc8349-gpio", },
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{ .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
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{ .compatible = "fsl,mpc8610-gpio", },
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{ .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
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{ .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
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{ .compatible = "fsl,pq3-gpio", },
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{ .compatible = "fsl,qoriq-gpio", },
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{}
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};
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static int mpc8xxx_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct mpc8xxx_gpio_chip *mpc8xxx_gc;
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struct gpio_chip *gc;
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const struct mpc8xxx_gpio_devtype *devtype =
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of_device_get_match_data(&pdev->dev);
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int ret;
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mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
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if (!mpc8xxx_gc)
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return -ENOMEM;
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platform_set_drvdata(pdev, mpc8xxx_gc);
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raw_spin_lock_init(&mpc8xxx_gc->lock);
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mpc8xxx_gc->regs = of_iomap(np, 0);
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if (!mpc8xxx_gc->regs)
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return -ENOMEM;
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gc = &mpc8xxx_gc->gc;
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gc->parent = &pdev->dev;
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if (of_property_read_bool(np, "little-endian")) {
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ret = bgpio_init(gc, &pdev->dev, 4,
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mpc8xxx_gc->regs + GPIO_DAT,
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NULL, NULL,
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mpc8xxx_gc->regs + GPIO_DIR, NULL,
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BGPIOF_BIG_ENDIAN);
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if (ret)
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goto err;
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dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
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} else {
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ret = bgpio_init(gc, &pdev->dev, 4,
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mpc8xxx_gc->regs + GPIO_DAT,
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NULL, NULL,
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mpc8xxx_gc->regs + GPIO_DIR, NULL,
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BGPIOF_BIG_ENDIAN
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| BGPIOF_BIG_ENDIAN_BYTE_ORDER);
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if (ret)
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goto err;
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dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
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}
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mpc8xxx_gc->direction_output = gc->direction_output;
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if (!devtype)
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devtype = &mpc8xxx_gpio_devtype_default;
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/*
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* It's assumed that only a single type of gpio controller is available
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* on the current machine, so overwriting global data is fine.
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*/
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if (devtype->irq_set_type)
|
||
|
|
mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
|
||
|
|
|
||
|
|
if (devtype->gpio_dir_out)
|
||
|
|
gc->direction_output = devtype->gpio_dir_out;
|
||
|
|
if (devtype->gpio_get)
|
||
|
|
gc->get = devtype->gpio_get;
|
||
|
|
|
||
|
|
gc->to_irq = mpc8xxx_gpio_to_irq;
|
||
|
|
|
||
|
|
ret = gpiochip_add_data(gc, mpc8xxx_gc);
|
||
|
|
if (ret) {
|
||
|
|
pr_err("%s: GPIO chip registration failed with status %d\n",
|
||
|
|
np->full_name, ret);
|
||
|
|
goto err;
|
||
|
|
}
|
||
|
|
|
||
|
|
mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
|
||
|
|
if (!mpc8xxx_gc->irqn)
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
|
||
|
|
&mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
|
||
|
|
if (!mpc8xxx_gc->irq)
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
/* ack and mask all irqs */
|
||
|
|
gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
|
||
|
|
gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
|
||
|
|
|
||
|
|
irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
|
||
|
|
mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
|
||
|
|
return 0;
|
||
|
|
err:
|
||
|
|
iounmap(mpc8xxx_gc->regs);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int mpc8xxx_remove(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
|
||
|
|
|
||
|
|
if (mpc8xxx_gc->irq) {
|
||
|
|
irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
|
||
|
|
irq_domain_remove(mpc8xxx_gc->irq);
|
||
|
|
}
|
||
|
|
|
||
|
|
gpiochip_remove(&mpc8xxx_gc->gc);
|
||
|
|
iounmap(mpc8xxx_gc->regs);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct platform_driver mpc8xxx_plat_driver = {
|
||
|
|
.probe = mpc8xxx_probe,
|
||
|
|
.remove = mpc8xxx_remove,
|
||
|
|
.driver = {
|
||
|
|
.name = "gpio-mpc8xxx",
|
||
|
|
.of_match_table = mpc8xxx_gpio_ids,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init mpc8xxx_init(void)
|
||
|
|
{
|
||
|
|
return platform_driver_register(&mpc8xxx_plat_driver);
|
||
|
|
}
|
||
|
|
|
||
|
|
arch_initcall(mpc8xxx_init);
|