395 lines
10 KiB
C
395 lines
10 KiB
C
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/*
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* Copyright 2007-8 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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*/
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#include <linux/export.h>
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#include <drm/drmP.h>
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#include <drm/drm_edid.h>
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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#include "amdgpu_i2c.h"
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#include "amdgpu_atombios.h"
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#include "atom.h"
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#include "atombios_dp.h"
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#include "atombios_i2c.h"
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/* bit banging i2c */
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static int amdgpu_i2c_pre_xfer(struct i2c_adapter *i2c_adap)
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{
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struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
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struct amdgpu_device *adev = i2c->dev->dev_private;
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struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
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uint32_t temp;
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mutex_lock(&i2c->mutex);
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/* switch the pads to ddc mode */
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if (rec->hw_capable) {
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temp = RREG32(rec->mask_clk_reg);
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temp &= ~(1 << 16);
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WREG32(rec->mask_clk_reg, temp);
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}
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/* clear the output pin values */
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temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
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WREG32(rec->a_clk_reg, temp);
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temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
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WREG32(rec->a_data_reg, temp);
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/* set the pins to input */
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temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
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WREG32(rec->en_clk_reg, temp);
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temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
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WREG32(rec->en_data_reg, temp);
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/* mask the gpio pins for software use */
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temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
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WREG32(rec->mask_clk_reg, temp);
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temp = RREG32(rec->mask_clk_reg);
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temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
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WREG32(rec->mask_data_reg, temp);
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temp = RREG32(rec->mask_data_reg);
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return 0;
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}
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static void amdgpu_i2c_post_xfer(struct i2c_adapter *i2c_adap)
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{
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struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
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struct amdgpu_device *adev = i2c->dev->dev_private;
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struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
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uint32_t temp;
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/* unmask the gpio pins for software use */
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temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
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WREG32(rec->mask_clk_reg, temp);
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temp = RREG32(rec->mask_clk_reg);
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temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
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WREG32(rec->mask_data_reg, temp);
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temp = RREG32(rec->mask_data_reg);
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mutex_unlock(&i2c->mutex);
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}
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static int amdgpu_i2c_get_clock(void *i2c_priv)
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{
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struct amdgpu_i2c_chan *i2c = i2c_priv;
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struct amdgpu_device *adev = i2c->dev->dev_private;
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struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
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uint32_t val;
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/* read the value off the pin */
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val = RREG32(rec->y_clk_reg);
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val &= rec->y_clk_mask;
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return (val != 0);
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}
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static int amdgpu_i2c_get_data(void *i2c_priv)
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{
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struct amdgpu_i2c_chan *i2c = i2c_priv;
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struct amdgpu_device *adev = i2c->dev->dev_private;
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struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
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uint32_t val;
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/* read the value off the pin */
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val = RREG32(rec->y_data_reg);
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val &= rec->y_data_mask;
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return (val != 0);
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}
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static void amdgpu_i2c_set_clock(void *i2c_priv, int clock)
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{
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struct amdgpu_i2c_chan *i2c = i2c_priv;
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struct amdgpu_device *adev = i2c->dev->dev_private;
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struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
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uint32_t val;
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/* set pin direction */
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val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
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val |= clock ? 0 : rec->en_clk_mask;
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WREG32(rec->en_clk_reg, val);
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}
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static void amdgpu_i2c_set_data(void *i2c_priv, int data)
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{
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struct amdgpu_i2c_chan *i2c = i2c_priv;
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struct amdgpu_device *adev = i2c->dev->dev_private;
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struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
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uint32_t val;
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/* set pin direction */
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val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
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val |= data ? 0 : rec->en_data_mask;
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WREG32(rec->en_data_reg, val);
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}
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static const struct i2c_algorithm amdgpu_atombios_i2c_algo = {
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.master_xfer = amdgpu_atombios_i2c_xfer,
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.functionality = amdgpu_atombios_i2c_func,
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};
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struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev,
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const struct amdgpu_i2c_bus_rec *rec,
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const char *name)
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{
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struct amdgpu_i2c_chan *i2c;
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int ret;
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/* don't add the mm_i2c bus unless hw_i2c is enabled */
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if (rec->mm_i2c && (amdgpu_hw_i2c == 0))
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return NULL;
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i2c = kzalloc(sizeof(struct amdgpu_i2c_chan), GFP_KERNEL);
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if (i2c == NULL)
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return NULL;
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i2c->rec = *rec;
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i2c->adapter.owner = THIS_MODULE;
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i2c->adapter.class = I2C_CLASS_DDC;
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i2c->adapter.dev.parent = &dev->pdev->dev;
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i2c->dev = dev;
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i2c_set_adapdata(&i2c->adapter, i2c);
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mutex_init(&i2c->mutex);
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if (rec->hw_capable &&
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amdgpu_hw_i2c) {
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/* hw i2c using atom */
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snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
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"AMDGPU i2c hw bus %s", name);
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i2c->adapter.algo = &amdgpu_atombios_i2c_algo;
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ret = i2c_add_adapter(&i2c->adapter);
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if (ret)
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goto out_free;
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} else {
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/* set the amdgpu bit adapter */
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snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
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"AMDGPU i2c bit bus %s", name);
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i2c->adapter.algo_data = &i2c->bit;
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i2c->bit.pre_xfer = amdgpu_i2c_pre_xfer;
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i2c->bit.post_xfer = amdgpu_i2c_post_xfer;
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i2c->bit.setsda = amdgpu_i2c_set_data;
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i2c->bit.setscl = amdgpu_i2c_set_clock;
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i2c->bit.getsda = amdgpu_i2c_get_data;
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i2c->bit.getscl = amdgpu_i2c_get_clock;
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i2c->bit.udelay = 10;
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i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */
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i2c->bit.data = i2c;
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ret = i2c_bit_add_bus(&i2c->adapter);
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if (ret) {
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DRM_ERROR("Failed to register bit i2c %s\n", name);
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goto out_free;
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}
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}
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return i2c;
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out_free:
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kfree(i2c);
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return NULL;
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}
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void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c)
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{
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if (!i2c)
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return;
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WARN_ON(i2c->has_aux);
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i2c_del_adapter(&i2c->adapter);
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kfree(i2c);
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}
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/* Add the default buses */
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void amdgpu_i2c_init(struct amdgpu_device *adev)
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{
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if (amdgpu_hw_i2c)
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DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n");
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if (adev->is_atom_bios)
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amdgpu_atombios_i2c_init(adev);
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}
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/* remove all the buses */
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void amdgpu_i2c_fini(struct amdgpu_device *adev)
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{
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int i;
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for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
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if (adev->i2c_bus[i]) {
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amdgpu_i2c_destroy(adev->i2c_bus[i]);
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adev->i2c_bus[i] = NULL;
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}
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}
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}
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/* Add additional buses */
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void amdgpu_i2c_add(struct amdgpu_device *adev,
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const struct amdgpu_i2c_bus_rec *rec,
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const char *name)
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{
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struct drm_device *dev = adev->ddev;
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int i;
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for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
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if (!adev->i2c_bus[i]) {
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adev->i2c_bus[i] = amdgpu_i2c_create(dev, rec, name);
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return;
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}
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}
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}
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/* looks up bus based on id */
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struct amdgpu_i2c_chan *
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amdgpu_i2c_lookup(struct amdgpu_device *adev,
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const struct amdgpu_i2c_bus_rec *i2c_bus)
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{
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int i;
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for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
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if (adev->i2c_bus[i] &&
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(adev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
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return adev->i2c_bus[i];
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}
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}
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return NULL;
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}
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static void amdgpu_i2c_get_byte(struct amdgpu_i2c_chan *i2c_bus,
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u8 slave_addr,
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u8 addr,
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u8 *val)
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{
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u8 out_buf[2];
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u8 in_buf[2];
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struct i2c_msg msgs[] = {
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{
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.addr = slave_addr,
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.flags = 0,
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.len = 1,
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.buf = out_buf,
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},
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{
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.addr = slave_addr,
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.flags = I2C_M_RD,
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.len = 1,
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.buf = in_buf,
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}
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};
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out_buf[0] = addr;
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out_buf[1] = 0;
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if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
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*val = in_buf[0];
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DRM_DEBUG("val = 0x%02x\n", *val);
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} else {
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DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
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addr, *val);
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}
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}
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static void amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus,
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u8 slave_addr,
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u8 addr,
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u8 val)
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{
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uint8_t out_buf[2];
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struct i2c_msg msg = {
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.addr = slave_addr,
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.flags = 0,
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.len = 2,
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.buf = out_buf,
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};
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out_buf[0] = addr;
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out_buf[1] = val;
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if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
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DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
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addr, val);
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}
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/* ddc router switching */
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void
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amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector *amdgpu_connector)
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{
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u8 val;
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if (!amdgpu_connector->router.ddc_valid)
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return;
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if (!amdgpu_connector->router_bus)
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return;
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|
|
||
|
|
amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
|
||
|
|
amdgpu_connector->router.i2c_addr,
|
||
|
|
0x3, &val);
|
||
|
|
val &= ~amdgpu_connector->router.ddc_mux_control_pin;
|
||
|
|
amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
|
||
|
|
amdgpu_connector->router.i2c_addr,
|
||
|
|
0x3, val);
|
||
|
|
amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
|
||
|
|
amdgpu_connector->router.i2c_addr,
|
||
|
|
0x1, &val);
|
||
|
|
val &= ~amdgpu_connector->router.ddc_mux_control_pin;
|
||
|
|
val |= amdgpu_connector->router.ddc_mux_state;
|
||
|
|
amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
|
||
|
|
amdgpu_connector->router.i2c_addr,
|
||
|
|
0x1, val);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* clock/data router switching */
|
||
|
|
void
|
||
|
|
amdgpu_i2c_router_select_cd_port(const struct amdgpu_connector *amdgpu_connector)
|
||
|
|
{
|
||
|
|
u8 val;
|
||
|
|
|
||
|
|
if (!amdgpu_connector->router.cd_valid)
|
||
|
|
return;
|
||
|
|
|
||
|
|
if (!amdgpu_connector->router_bus)
|
||
|
|
return;
|
||
|
|
|
||
|
|
amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
|
||
|
|
amdgpu_connector->router.i2c_addr,
|
||
|
|
0x3, &val);
|
||
|
|
val &= ~amdgpu_connector->router.cd_mux_control_pin;
|
||
|
|
amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
|
||
|
|
amdgpu_connector->router.i2c_addr,
|
||
|
|
0x3, val);
|
||
|
|
amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
|
||
|
|
amdgpu_connector->router.i2c_addr,
|
||
|
|
0x1, &val);
|
||
|
|
val &= ~amdgpu_connector->router.cd_mux_control_pin;
|
||
|
|
val |= amdgpu_connector->router.cd_mux_state;
|
||
|
|
amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
|
||
|
|
amdgpu_connector->router.i2c_addr,
|
||
|
|
0x1, val);
|
||
|
|
}
|