572 lines
14 KiB
C
572 lines
14 KiB
C
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/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <linux/irq.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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#include "amdgpu_ih.h"
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#include "atom.h"
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#include "amdgpu_connectors.h"
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#include <linux/pm_runtime.h>
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#define AMDGPU_WAIT_IDLE_TIMEOUT 200
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/*
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* Handle hotplug events outside the interrupt handler proper.
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*/
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/**
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* amdgpu_hotplug_work_func - display hotplug work handler
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*
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* @work: work struct
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*
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* This is the hot plug event work handler (all asics).
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* The work gets scheduled from the irq handler if there
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* was a hot plug interrupt. It walks the connector table
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* and calls the hotplug handler for each one, then sends
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* a drm hotplug event to alert userspace.
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*/
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static void amdgpu_hotplug_work_func(struct work_struct *work)
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{
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struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
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hotplug_work);
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struct drm_device *dev = adev->ddev;
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struct drm_mode_config *mode_config = &dev->mode_config;
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struct drm_connector *connector;
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mutex_lock(&mode_config->mutex);
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if (mode_config->num_connector) {
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list_for_each_entry(connector, &mode_config->connector_list, head)
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amdgpu_connector_hotplug(connector);
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}
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mutex_unlock(&mode_config->mutex);
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/* Just fire off a uevent and let userspace tell us what to do */
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drm_helper_hpd_irq_event(dev);
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}
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/**
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* amdgpu_irq_reset_work_func - execute gpu reset
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*
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* @work: work struct
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*
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* Execute scheduled gpu reset (cayman+).
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* This function is called when the irq handler
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* thinks we need a gpu reset.
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*/
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static void amdgpu_irq_reset_work_func(struct work_struct *work)
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{
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struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
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reset_work);
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amdgpu_gpu_reset(adev);
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}
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/* Disable *all* interrupts */
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static void amdgpu_irq_disable_all(struct amdgpu_device *adev)
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{
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unsigned long irqflags;
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unsigned i, j;
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int r;
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spin_lock_irqsave(&adev->irq.lock, irqflags);
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for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) {
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struct amdgpu_irq_src *src = adev->irq.sources[i];
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if (!src || !src->funcs->set || !src->num_types)
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continue;
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for (j = 0; j < src->num_types; ++j) {
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atomic_set(&src->enabled_types[j], 0);
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r = src->funcs->set(adev, src, j,
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AMDGPU_IRQ_STATE_DISABLE);
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if (r)
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DRM_ERROR("error disabling interrupt (%d)\n",
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r);
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}
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}
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spin_unlock_irqrestore(&adev->irq.lock, irqflags);
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}
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/**
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* amdgpu_irq_preinstall - drm irq preinstall callback
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*
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* @dev: drm dev pointer
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*
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* Gets the hw ready to enable irqs (all asics).
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* This function disables all interrupt sources on the GPU.
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*/
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void amdgpu_irq_preinstall(struct drm_device *dev)
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{
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struct amdgpu_device *adev = dev->dev_private;
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/* Disable *all* interrupts */
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amdgpu_irq_disable_all(adev);
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/* Clear bits */
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amdgpu_ih_process(adev);
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}
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/**
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* amdgpu_irq_postinstall - drm irq preinstall callback
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*
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* @dev: drm dev pointer
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*
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* Handles stuff to be done after enabling irqs (all asics).
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* Returns 0 on success.
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*/
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int amdgpu_irq_postinstall(struct drm_device *dev)
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{
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dev->max_vblank_count = 0x00ffffff;
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return 0;
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}
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/**
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* amdgpu_irq_uninstall - drm irq uninstall callback
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*
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* @dev: drm dev pointer
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*
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* This function disables all interrupt sources on the GPU (all asics).
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*/
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void amdgpu_irq_uninstall(struct drm_device *dev)
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{
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struct amdgpu_device *adev = dev->dev_private;
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if (adev == NULL) {
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return;
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}
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amdgpu_irq_disable_all(adev);
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}
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/**
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* amdgpu_irq_handler - irq handler
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*
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* @int irq, void *arg: args
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*
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* This is the irq handler for the amdgpu driver (all asics).
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*/
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irqreturn_t amdgpu_irq_handler(int irq, void *arg)
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{
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struct drm_device *dev = (struct drm_device *) arg;
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struct amdgpu_device *adev = dev->dev_private;
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irqreturn_t ret;
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ret = amdgpu_ih_process(adev);
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if (ret == IRQ_HANDLED)
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pm_runtime_mark_last_busy(dev->dev);
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return ret;
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}
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/**
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* amdgpu_msi_ok - asic specific msi checks
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*
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* @adev: amdgpu device pointer
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*
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* Handles asic specific MSI checks to determine if
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* MSIs should be enabled on a particular chip (all asics).
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* Returns true if MSIs should be enabled, false if MSIs
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* should not be enabled.
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*/
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static bool amdgpu_msi_ok(struct amdgpu_device *adev)
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{
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/* force MSI on */
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if (amdgpu_msi == 1)
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return true;
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else if (amdgpu_msi == 0)
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return false;
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return true;
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}
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/**
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* amdgpu_irq_init - init driver interrupt info
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*
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* @adev: amdgpu device pointer
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*
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* Sets up the work irq handlers, vblank init, MSIs, etc. (all asics).
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* Returns 0 for success, error for failure.
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*/
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int amdgpu_irq_init(struct amdgpu_device *adev)
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{
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int r = 0;
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spin_lock_init(&adev->irq.lock);
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r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
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if (r) {
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return r;
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}
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/* enable msi */
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adev->irq.msi_enabled = false;
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if (amdgpu_msi_ok(adev)) {
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int ret = pci_enable_msi(adev->pdev);
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if (!ret) {
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adev->irq.msi_enabled = true;
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dev_info(adev->dev, "amdgpu: using MSI.\n");
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}
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}
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INIT_WORK(&adev->hotplug_work, amdgpu_hotplug_work_func);
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INIT_WORK(&adev->reset_work, amdgpu_irq_reset_work_func);
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adev->irq.installed = true;
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r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
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if (r) {
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adev->irq.installed = false;
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flush_work(&adev->hotplug_work);
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cancel_work_sync(&adev->reset_work);
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return r;
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}
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DRM_INFO("amdgpu: irq initialized.\n");
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return 0;
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}
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/**
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* amdgpu_irq_fini - tear down driver interrupt info
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*
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* @adev: amdgpu device pointer
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*
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* Tears down the work irq handlers, vblank handlers, MSIs, etc. (all asics).
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*/
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void amdgpu_irq_fini(struct amdgpu_device *adev)
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{
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unsigned i;
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drm_vblank_cleanup(adev->ddev);
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if (adev->irq.installed) {
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drm_irq_uninstall(adev->ddev);
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adev->irq.installed = false;
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if (adev->irq.msi_enabled)
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pci_disable_msi(adev->pdev);
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flush_work(&adev->hotplug_work);
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cancel_work_sync(&adev->reset_work);
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}
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for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) {
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struct amdgpu_irq_src *src = adev->irq.sources[i];
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if (!src)
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continue;
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kfree(src->enabled_types);
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src->enabled_types = NULL;
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if (src->data) {
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kfree(src->data);
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kfree(src);
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adev->irq.sources[i] = NULL;
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}
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}
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}
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/**
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* amdgpu_irq_add_id - register irq source
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*
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* @adev: amdgpu device pointer
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* @src_id: source id for this source
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* @source: irq source
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*
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*/
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int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id,
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struct amdgpu_irq_src *source)
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{
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if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
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return -EINVAL;
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if (adev->irq.sources[src_id] != NULL)
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return -EINVAL;
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if (!source->funcs)
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return -EINVAL;
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if (source->num_types && !source->enabled_types) {
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atomic_t *types;
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types = kcalloc(source->num_types, sizeof(atomic_t),
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GFP_KERNEL);
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if (!types)
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return -ENOMEM;
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source->enabled_types = types;
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}
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adev->irq.sources[src_id] = source;
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return 0;
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}
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/**
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* amdgpu_irq_dispatch - dispatch irq to IP blocks
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*
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* @adev: amdgpu device pointer
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* @entry: interrupt vector
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*
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* Dispatches the irq to the different IP blocks
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*/
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void amdgpu_irq_dispatch(struct amdgpu_device *adev,
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struct amdgpu_iv_entry *entry)
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{
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unsigned src_id = entry->src_id;
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struct amdgpu_irq_src *src;
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int r;
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if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
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DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
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return;
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}
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if (adev->irq.virq[src_id]) {
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generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
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} else {
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src = adev->irq.sources[src_id];
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if (!src) {
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DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
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return;
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}
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r = src->funcs->process(adev, src, entry);
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if (r)
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DRM_ERROR("error processing interrupt (%d)\n", r);
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}
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}
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/**
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* amdgpu_irq_update - update hw interrupt state
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*
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* @adev: amdgpu device pointer
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* @src: interrupt src you want to enable
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* @type: type of interrupt you want to update
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*
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* Updates the interrupt state for a specific src (all asics).
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*/
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int amdgpu_irq_update(struct amdgpu_device *adev,
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struct amdgpu_irq_src *src, unsigned type)
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{
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unsigned long irqflags;
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enum amdgpu_interrupt_state state;
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int r;
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spin_lock_irqsave(&adev->irq.lock, irqflags);
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/* we need to determine after taking the lock, otherwise
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we might disable just enabled interrupts again */
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if (amdgpu_irq_enabled(adev, src, type))
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state = AMDGPU_IRQ_STATE_ENABLE;
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else
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state = AMDGPU_IRQ_STATE_DISABLE;
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||
|
|
r = src->funcs->set(adev, src, type, state);
|
||
|
|
spin_unlock_irqrestore(&adev->irq.lock, irqflags);
|
||
|
|
return r;
|
||
|
|
}
|
||
|
|
|
||
|
|
void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
|
||
|
|
{
|
||
|
|
int i, j;
|
||
|
|
for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; i++) {
|
||
|
|
struct amdgpu_irq_src *src = adev->irq.sources[i];
|
||
|
|
if (!src)
|
||
|
|
continue;
|
||
|
|
for (j = 0; j < src->num_types; j++)
|
||
|
|
amdgpu_irq_update(adev, src, j);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* amdgpu_irq_get - enable interrupt
|
||
|
|
*
|
||
|
|
* @adev: amdgpu device pointer
|
||
|
|
* @src: interrupt src you want to enable
|
||
|
|
* @type: type of interrupt you want to enable
|
||
|
|
*
|
||
|
|
* Enables the interrupt type for a specific src (all asics).
|
||
|
|
*/
|
||
|
|
int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
|
||
|
|
unsigned type)
|
||
|
|
{
|
||
|
|
if (!adev->ddev->irq_enabled)
|
||
|
|
return -ENOENT;
|
||
|
|
|
||
|
|
if (type >= src->num_types)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
if (!src->enabled_types || !src->funcs->set)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
if (atomic_inc_return(&src->enabled_types[type]) == 1)
|
||
|
|
return amdgpu_irq_update(adev, src, type);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool amdgpu_irq_get_delayed(struct amdgpu_device *adev,
|
||
|
|
struct amdgpu_irq_src *src,
|
||
|
|
unsigned type)
|
||
|
|
{
|
||
|
|
if ((type >= src->num_types) || !src->enabled_types)
|
||
|
|
return false;
|
||
|
|
return atomic_inc_return(&src->enabled_types[type]) == 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* amdgpu_irq_put - disable interrupt
|
||
|
|
*
|
||
|
|
* @adev: amdgpu device pointer
|
||
|
|
* @src: interrupt src you want to disable
|
||
|
|
* @type: type of interrupt you want to disable
|
||
|
|
*
|
||
|
|
* Disables the interrupt type for a specific src (all asics).
|
||
|
|
*/
|
||
|
|
int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
|
||
|
|
unsigned type)
|
||
|
|
{
|
||
|
|
if (!adev->ddev->irq_enabled)
|
||
|
|
return -ENOENT;
|
||
|
|
|
||
|
|
if (type >= src->num_types)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
if (!src->enabled_types || !src->funcs->set)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
if (atomic_dec_and_test(&src->enabled_types[type]))
|
||
|
|
return amdgpu_irq_update(adev, src, type);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* amdgpu_irq_enabled - test if irq is enabled or not
|
||
|
|
*
|
||
|
|
* @adev: amdgpu device pointer
|
||
|
|
* @idx: interrupt src you want to test
|
||
|
|
*
|
||
|
|
* Tests if the given interrupt source is enabled or not
|
||
|
|
*/
|
||
|
|
bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
|
||
|
|
unsigned type)
|
||
|
|
{
|
||
|
|
if (!adev->ddev->irq_enabled)
|
||
|
|
return false;
|
||
|
|
|
||
|
|
if (type >= src->num_types)
|
||
|
|
return false;
|
||
|
|
|
||
|
|
if (!src->enabled_types || !src->funcs->set)
|
||
|
|
return false;
|
||
|
|
|
||
|
|
return !!atomic_read(&src->enabled_types[type]);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* gen irq */
|
||
|
|
static void amdgpu_irq_mask(struct irq_data *irqd)
|
||
|
|
{
|
||
|
|
/* XXX */
|
||
|
|
}
|
||
|
|
|
||
|
|
static void amdgpu_irq_unmask(struct irq_data *irqd)
|
||
|
|
{
|
||
|
|
/* XXX */
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct irq_chip amdgpu_irq_chip = {
|
||
|
|
.name = "amdgpu-ih",
|
||
|
|
.irq_mask = amdgpu_irq_mask,
|
||
|
|
.irq_unmask = amdgpu_irq_unmask,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int amdgpu_irqdomain_map(struct irq_domain *d,
|
||
|
|
unsigned int irq, irq_hw_number_t hwirq)
|
||
|
|
{
|
||
|
|
if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
|
||
|
|
return -EPERM;
|
||
|
|
|
||
|
|
irq_set_chip_and_handler(irq,
|
||
|
|
&amdgpu_irq_chip, handle_simple_irq);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
|
||
|
|
.map = amdgpu_irqdomain_map,
|
||
|
|
};
|
||
|
|
|
||
|
|
/**
|
||
|
|
* amdgpu_irq_add_domain - create a linear irq domain
|
||
|
|
*
|
||
|
|
* @adev: amdgpu device pointer
|
||
|
|
*
|
||
|
|
* Create an irq domain for GPU interrupt sources
|
||
|
|
* that may be driven by another driver (e.g., ACP).
|
||
|
|
*/
|
||
|
|
int amdgpu_irq_add_domain(struct amdgpu_device *adev)
|
||
|
|
{
|
||
|
|
adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
|
||
|
|
&amdgpu_hw_irqdomain_ops, adev);
|
||
|
|
if (!adev->irq.domain) {
|
||
|
|
DRM_ERROR("GPU irq add domain failed\n");
|
||
|
|
return -ENODEV;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* amdgpu_irq_remove_domain - remove the irq domain
|
||
|
|
*
|
||
|
|
* @adev: amdgpu device pointer
|
||
|
|
*
|
||
|
|
* Remove the irq domain for GPU interrupt sources
|
||
|
|
* that may be driven by another driver (e.g., ACP).
|
||
|
|
*/
|
||
|
|
void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
|
||
|
|
{
|
||
|
|
if (adev->irq.domain) {
|
||
|
|
irq_domain_remove(adev->irq.domain);
|
||
|
|
adev->irq.domain = NULL;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* amdgpu_irq_create_mapping - create a mapping between a domain irq and a
|
||
|
|
* Linux irq
|
||
|
|
*
|
||
|
|
* @adev: amdgpu device pointer
|
||
|
|
* @src_id: IH source id
|
||
|
|
*
|
||
|
|
* Create a mapping between a domain irq (GPU IH src id) and a Linux irq
|
||
|
|
* Use this for components that generate a GPU interrupt, but are driven
|
||
|
|
* by a different driver (e.g., ACP).
|
||
|
|
* Returns the Linux irq.
|
||
|
|
*/
|
||
|
|
unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id)
|
||
|
|
{
|
||
|
|
adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
|
||
|
|
|
||
|
|
return adev->irq.virq[src_id];
|
||
|
|
}
|