316 lines
12 KiB
C
316 lines
12 KiB
C
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/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef PP_ATOMVOLTAGECTRL_H
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#define PP_ATOMVOLTAGECTRL_H
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#include "hwmgr.h"
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#define MEM_TYPE_GDDR5 0x50
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#define MEM_TYPE_GDDR4 0x40
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#define MEM_TYPE_GDDR3 0x30
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#define MEM_TYPE_DDR2 0x20
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#define MEM_TYPE_GDDR1 0x10
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#define MEM_TYPE_DDR3 0xb0
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#define MEM_TYPE_MASK 0xF0
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/* As returned from PowerConnectorDetectionTable. */
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#define PP_ATOM_POWER_BUDGET_DISABLE_OVERDRIVE 0x80
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#define PP_ATOM_POWER_BUDGET_SHOW_WARNING 0x40
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#define PP_ATOM_POWER_BUDGET_SHOW_WAIVER 0x20
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#define PP_ATOM_POWER_POWER_BUDGET_BEHAVIOUR 0x0F
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/* New functions for Evergreen and beyond. */
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#define PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES 32
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struct pp_atomctrl_clock_dividers {
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uint32_t pll_post_divider;
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uint32_t pll_feedback_divider;
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uint32_t pll_ref_divider;
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bool enable_post_divider;
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};
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typedef struct pp_atomctrl_clock_dividers pp_atomctrl_clock_dividers;
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union pp_atomctrl_tcipll_fb_divider {
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struct {
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uint32_t ul_fb_div_frac : 14;
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uint32_t ul_fb_div : 12;
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uint32_t un_used : 6;
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};
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uint32_t ul_fb_divider;
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};
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typedef union pp_atomctrl_tcipll_fb_divider pp_atomctrl_tcipll_fb_divider;
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struct pp_atomctrl_clock_dividers_rv730 {
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uint32_t pll_post_divider;
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pp_atomctrl_tcipll_fb_divider mpll_feedback_divider;
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uint32_t pll_ref_divider;
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bool enable_post_divider;
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bool enable_dithen;
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uint32_t vco_mode;
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};
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typedef struct pp_atomctrl_clock_dividers_rv730 pp_atomctrl_clock_dividers_rv730;
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struct pp_atomctrl_clock_dividers_kong {
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uint32_t pll_post_divider;
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uint32_t real_clock;
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};
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typedef struct pp_atomctrl_clock_dividers_kong pp_atomctrl_clock_dividers_kong;
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struct pp_atomctrl_clock_dividers_ci {
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uint32_t pll_post_divider; /* post divider value */
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uint32_t real_clock;
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pp_atomctrl_tcipll_fb_divider ul_fb_div; /* Output Parameter: PLL FB divider */
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uint8_t uc_pll_ref_div; /* Output Parameter: PLL ref divider */
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uint8_t uc_pll_post_div; /* Output Parameter: PLL post divider */
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uint8_t uc_pll_cntl_flag; /*Output Flags: control flag */
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};
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typedef struct pp_atomctrl_clock_dividers_ci pp_atomctrl_clock_dividers_ci;
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struct pp_atomctrl_clock_dividers_vi {
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uint32_t pll_post_divider; /* post divider value */
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uint32_t real_clock;
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pp_atomctrl_tcipll_fb_divider ul_fb_div; /*Output Parameter: PLL FB divider */
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uint8_t uc_pll_ref_div; /*Output Parameter: PLL ref divider */
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uint8_t uc_pll_post_div; /*Output Parameter: PLL post divider */
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uint8_t uc_pll_cntl_flag; /*Output Flags: control flag */
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};
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typedef struct pp_atomctrl_clock_dividers_vi pp_atomctrl_clock_dividers_vi;
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struct pp_atomctrl_clock_dividers_ai {
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u16 usSclk_fcw_frac;
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u16 usSclk_fcw_int;
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u8 ucSclkPostDiv;
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u8 ucSclkVcoMode;
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u8 ucSclkPllRange;
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u8 ucSscEnable;
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u16 usSsc_fcw1_frac;
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u16 usSsc_fcw1_int;
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u16 usReserved;
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u16 usPcc_fcw_int;
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u16 usSsc_fcw_slew_frac;
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u16 usPcc_fcw_slew_frac;
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};
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typedef struct pp_atomctrl_clock_dividers_ai pp_atomctrl_clock_dividers_ai;
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union pp_atomctrl_s_mpll_fb_divider {
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struct {
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uint32_t cl_kf : 12;
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uint32_t clk_frac : 12;
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uint32_t un_used : 8;
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};
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uint32_t ul_fb_divider;
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};
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typedef union pp_atomctrl_s_mpll_fb_divider pp_atomctrl_s_mpll_fb_divider;
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enum pp_atomctrl_spread_spectrum_mode {
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pp_atomctrl_spread_spectrum_mode_down = 0,
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pp_atomctrl_spread_spectrum_mode_center
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};
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typedef enum pp_atomctrl_spread_spectrum_mode pp_atomctrl_spread_spectrum_mode;
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struct pp_atomctrl_memory_clock_param {
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pp_atomctrl_s_mpll_fb_divider mpll_fb_divider;
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uint32_t mpll_post_divider;
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uint32_t bw_ctrl;
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uint32_t dll_speed;
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uint32_t vco_mode;
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uint32_t yclk_sel;
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uint32_t qdr;
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uint32_t half_rate;
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};
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typedef struct pp_atomctrl_memory_clock_param pp_atomctrl_memory_clock_param;
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struct pp_atomctrl_internal_ss_info {
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uint32_t speed_spectrum_percentage; /* in 1/100 percentage */
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uint32_t speed_spectrum_rate; /* in KHz */
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pp_atomctrl_spread_spectrum_mode speed_spectrum_mode;
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};
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typedef struct pp_atomctrl_internal_ss_info pp_atomctrl_internal_ss_info;
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#ifndef NUMBER_OF_M3ARB_PARAMS
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#define NUMBER_OF_M3ARB_PARAMS 3
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#endif
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#ifndef NUMBER_OF_M3ARB_PARAM_SETS
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#define NUMBER_OF_M3ARB_PARAM_SETS 10
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#endif
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struct pp_atomctrl_kong_system_info {
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uint32_t ul_bootup_uma_clock; /* in 10kHz unit */
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uint16_t us_max_nb_voltage; /* high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */
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uint16_t us_min_nb_voltage; /* low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */
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uint16_t us_bootup_nb_voltage; /* boot up NB voltage */
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uint8_t uc_htc_tmp_lmt; /* bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD */
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uint8_t uc_tj_offset; /* bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD */
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/* 0: default 1: uvd 2: fs-3d */
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uint32_t ul_csr_m3_srb_cntl[NUMBER_OF_M3ARB_PARAM_SETS][NUMBER_OF_M3ARB_PARAMS];/* arrays with values for CSR M3 arbiter for default */
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};
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typedef struct pp_atomctrl_kong_system_info pp_atomctrl_kong_system_info;
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struct pp_atomctrl_memory_info {
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uint8_t memory_vendor;
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uint8_t memory_type;
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};
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typedef struct pp_atomctrl_memory_info pp_atomctrl_memory_info;
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#define MAX_AC_TIMING_ENTRIES 16
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struct pp_atomctrl_memory_clock_range_table {
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uint8_t num_entries;
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uint8_t rsv[3];
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uint32_t mclk[MAX_AC_TIMING_ENTRIES];
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};
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typedef struct pp_atomctrl_memory_clock_range_table pp_atomctrl_memory_clock_range_table;
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struct pp_atomctrl_voltage_table_entry {
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uint16_t value;
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uint32_t smio_low;
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};
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typedef struct pp_atomctrl_voltage_table_entry pp_atomctrl_voltage_table_entry;
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struct pp_atomctrl_voltage_table {
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uint32_t count;
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uint32_t mask_low;
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uint32_t phase_delay; /* Used for ATOM_GPIO_VOLTAGE_OBJECT_V3 and later */
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pp_atomctrl_voltage_table_entry entries[PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES];
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};
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typedef struct pp_atomctrl_voltage_table pp_atomctrl_voltage_table;
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#define VBIOS_MC_REGISTER_ARRAY_SIZE 32
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#define VBIOS_MAX_AC_TIMING_ENTRIES 20
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struct pp_atomctrl_mc_reg_entry {
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uint32_t mclk_max;
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uint32_t mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
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};
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typedef struct pp_atomctrl_mc_reg_entry pp_atomctrl_mc_reg_entry;
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struct pp_atomctrl_mc_register_address {
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uint16_t s1;
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uint8_t uc_pre_reg_data;
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};
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typedef struct pp_atomctrl_mc_register_address pp_atomctrl_mc_register_address;
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#define MAX_SCLK_RANGE 8
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struct pp_atom_ctrl_sclk_range_table_entry{
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uint8_t ucVco_setting;
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uint8_t ucPostdiv;
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uint16_t usFcw_pcc;
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uint16_t usFcw_trans_upper;
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uint16_t usRcw_trans_lower;
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};
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struct pp_atom_ctrl_sclk_range_table{
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struct pp_atom_ctrl_sclk_range_table_entry entry[MAX_SCLK_RANGE];
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};
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struct pp_atomctrl_mc_reg_table {
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uint8_t last; /* number of registers */
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uint8_t num_entries; /* number of AC timing entries */
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pp_atomctrl_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
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pp_atomctrl_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
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};
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typedef struct pp_atomctrl_mc_reg_table pp_atomctrl_mc_reg_table;
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struct pp_atomctrl_gpio_pin_assignment {
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uint16_t us_gpio_pin_aindex;
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uint8_t uc_gpio_pin_bit_shift;
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};
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typedef struct pp_atomctrl_gpio_pin_assignment pp_atomctrl_gpio_pin_assignment;
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struct pp_atom_ctrl__avfs_parameters {
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uint32_t ulAVFS_meanNsigma_Acontant0;
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uint32_t ulAVFS_meanNsigma_Acontant1;
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uint32_t ulAVFS_meanNsigma_Acontant2;
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uint16_t usAVFS_meanNsigma_DC_tol_sigma;
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uint16_t usAVFS_meanNsigma_Platform_mean;
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uint16_t usAVFS_meanNsigma_Platform_sigma;
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uint32_t ulGB_VDROOP_TABLE_CKSOFF_a0;
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uint32_t ulGB_VDROOP_TABLE_CKSOFF_a1;
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uint32_t ulGB_VDROOP_TABLE_CKSOFF_a2;
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uint32_t ulGB_VDROOP_TABLE_CKSON_a0;
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uint32_t ulGB_VDROOP_TABLE_CKSON_a1;
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uint32_t ulGB_VDROOP_TABLE_CKSON_a2;
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uint32_t ulAVFSGB_FUSE_TABLE_CKSOFF_m1;
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uint16_t usAVFSGB_FUSE_TABLE_CKSOFF_m2;
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uint32_t ulAVFSGB_FUSE_TABLE_CKSOFF_b;
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uint32_t ulAVFSGB_FUSE_TABLE_CKSON_m1;
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uint16_t usAVFSGB_FUSE_TABLE_CKSON_m2;
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uint32_t ulAVFSGB_FUSE_TABLE_CKSON_b;
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uint16_t usMaxVoltage_0_25mv;
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uint8_t ucEnableGB_VDROOP_TABLE_CKSOFF;
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uint8_t ucEnableGB_VDROOP_TABLE_CKSON;
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uint8_t ucEnableGB_FUSE_TABLE_CKSOFF;
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uint8_t ucEnableGB_FUSE_TABLE_CKSON;
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uint16_t usPSM_Age_ComFactor;
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uint8_t ucEnableApplyAVFS_CKS_OFF_Voltage;
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uint8_t ucReserved;
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};
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extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment);
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extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
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extern int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr, uint16_t virtual_voltage_id, uint16_t *voltage);
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extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr);
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extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo);
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extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo);
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extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table);
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extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
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extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr);
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extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode);
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extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
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extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
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extern bool atomctrl_is_voltage_controled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode);
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extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table);
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extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
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uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param);
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extern int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
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uint32_t clock_value,
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pp_atomctrl_clock_dividers_kong *dividers);
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extern int atomctrl_read_efuse(void *device, uint16_t start_index,
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uint16_t end_index, uint32_t mask, uint32_t *efuse);
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extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
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uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug);
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extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers);
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extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
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uint8_t level);
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extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
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uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage);
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extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table);
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extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param);
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#endif
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