369 lines
9.0 KiB
C
369 lines
9.0 KiB
C
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/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <drm/amdgpu_drm.h>
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#include "pp_instance.h"
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#include "smumgr.h"
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#include "cgs_common.h"
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#include "linux/delay.h"
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int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
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{
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struct pp_smumgr *smumgr;
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if ((handle == NULL) || (pp_init == NULL))
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return -EINVAL;
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smumgr = kzalloc(sizeof(struct pp_smumgr), GFP_KERNEL);
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if (smumgr == NULL)
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return -ENOMEM;
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smumgr->device = pp_init->device;
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smumgr->chip_family = pp_init->chip_family;
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smumgr->chip_id = pp_init->chip_id;
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smumgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
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smumgr->reload_fw = 1;
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handle->smu_mgr = smumgr;
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switch (smumgr->chip_family) {
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case AMDGPU_FAMILY_CZ:
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cz_smum_init(smumgr);
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break;
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case AMDGPU_FAMILY_VI:
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switch (smumgr->chip_id) {
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case CHIP_TOPAZ:
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iceland_smum_init(smumgr);
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break;
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case CHIP_TONGA:
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tonga_smum_init(smumgr);
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break;
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case CHIP_FIJI:
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fiji_smum_init(smumgr);
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break;
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case CHIP_POLARIS11:
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case CHIP_POLARIS10:
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polaris10_smum_init(smumgr);
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break;
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default:
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return -EINVAL;
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}
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break;
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default:
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kfree(smumgr);
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return -EINVAL;
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}
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return 0;
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}
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int smum_fini(struct pp_smumgr *smumgr)
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{
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kfree(smumgr->device);
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kfree(smumgr);
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return 0;
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}
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int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
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void *input, void *output, void *storage, int result)
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{
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if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable)
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return hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable(hwmgr);
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return 0;
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}
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int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
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void *input, void *output, void *storage, int result)
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{
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if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table)
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return hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table(hwmgr);
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return 0;
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}
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int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr)
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{
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if (NULL != hwmgr->smumgr->smumgr_funcs->update_sclk_threshold)
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return hwmgr->smumgr->smumgr_funcs->update_sclk_threshold(hwmgr);
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return 0;
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}
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int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
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{
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if (NULL != hwmgr->smumgr->smumgr_funcs->update_smc_table)
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return hwmgr->smumgr->smumgr_funcs->update_smc_table(hwmgr, type);
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return 0;
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}
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uint32_t smum_get_offsetof(struct pp_smumgr *smumgr, uint32_t type, uint32_t member)
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{
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if (NULL != smumgr->smumgr_funcs->get_offsetof)
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return smumgr->smumgr_funcs->get_offsetof(type, member);
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return 0;
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}
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int smum_process_firmware_header(struct pp_hwmgr *hwmgr)
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{
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if (NULL != hwmgr->smumgr->smumgr_funcs->process_firmware_header)
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return hwmgr->smumgr->smumgr_funcs->process_firmware_header(hwmgr);
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return 0;
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}
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int smum_get_argument(struct pp_smumgr *smumgr)
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{
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if (NULL != smumgr->smumgr_funcs->get_argument)
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return smumgr->smumgr_funcs->get_argument(smumgr);
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return 0;
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}
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uint32_t smum_get_mac_definition(struct pp_smumgr *smumgr, uint32_t value)
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{
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if (NULL != smumgr->smumgr_funcs->get_mac_definition)
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return smumgr->smumgr_funcs->get_mac_definition(value);
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return 0;
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}
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int smum_download_powerplay_table(struct pp_smumgr *smumgr,
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void **table)
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{
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if (NULL != smumgr->smumgr_funcs->download_pptable_settings)
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return smumgr->smumgr_funcs->download_pptable_settings(smumgr,
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table);
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return 0;
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}
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int smum_upload_powerplay_table(struct pp_smumgr *smumgr)
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{
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if (NULL != smumgr->smumgr_funcs->upload_pptable_settings)
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return smumgr->smumgr_funcs->upload_pptable_settings(smumgr);
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return 0;
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}
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int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
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{
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if (smumgr == NULL || smumgr->smumgr_funcs->send_msg_to_smc == NULL)
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return -EINVAL;
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return smumgr->smumgr_funcs->send_msg_to_smc(smumgr, msg);
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}
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int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
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uint16_t msg, uint32_t parameter)
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{
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if (smumgr == NULL ||
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smumgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL)
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return -EINVAL;
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return smumgr->smumgr_funcs->send_msg_to_smc_with_parameter(
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smumgr, msg, parameter);
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}
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/*
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* Returns once the part of the register indicated by the mask has
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* reached the given value.
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*/
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int smum_wait_on_register(struct pp_smumgr *smumgr,
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uint32_t index,
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uint32_t value, uint32_t mask)
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{
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uint32_t i;
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uint32_t cur_value;
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if (smumgr == NULL || smumgr->device == NULL)
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return -EINVAL;
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for (i = 0; i < smumgr->usec_timeout; i++) {
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cur_value = cgs_read_register(smumgr->device, index);
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if ((cur_value & mask) == (value & mask))
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break;
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udelay(1);
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}
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/* timeout means wrong logic*/
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if (i == smumgr->usec_timeout)
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return -1;
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return 0;
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}
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int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
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uint32_t index,
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uint32_t value, uint32_t mask)
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{
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uint32_t i;
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uint32_t cur_value;
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if (smumgr == NULL)
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return -EINVAL;
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for (i = 0; i < smumgr->usec_timeout; i++) {
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cur_value = cgs_read_register(smumgr->device,
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index);
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if ((cur_value & mask) != (value & mask))
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break;
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udelay(1);
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}
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/* timeout means wrong logic */
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if (i == smumgr->usec_timeout)
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return -1;
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return 0;
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}
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/*
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* Returns once the part of the register indicated by the mask
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* has reached the given value.The indirect space is described by
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* giving the memory-mapped index of the indirect index register.
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*/
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int smum_wait_on_indirect_register(struct pp_smumgr *smumgr,
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uint32_t indirect_port,
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uint32_t index,
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uint32_t value,
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uint32_t mask)
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{
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if (smumgr == NULL || smumgr->device == NULL)
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return -EINVAL;
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cgs_write_register(smumgr->device, indirect_port, index);
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return smum_wait_on_register(smumgr, indirect_port + 1,
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mask, value);
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}
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void smum_wait_for_indirect_register_unequal(
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struct pp_smumgr *smumgr,
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uint32_t indirect_port,
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uint32_t index,
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uint32_t value,
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uint32_t mask)
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{
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if (smumgr == NULL || smumgr->device == NULL)
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return;
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cgs_write_register(smumgr->device, indirect_port, index);
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smum_wait_for_register_unequal(smumgr, indirect_port + 1,
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value, mask);
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}
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int smu_allocate_memory(void *device, uint32_t size,
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enum cgs_gpu_mem_type type,
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uint32_t byte_align, uint64_t *mc_addr,
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void **kptr, void *handle)
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{
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int ret = 0;
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cgs_handle_t cgs_handle;
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if (device == NULL || handle == NULL ||
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mc_addr == NULL || kptr == NULL)
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return -EINVAL;
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ret = cgs_alloc_gpu_mem(device, type, size, byte_align,
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0, 0, (cgs_handle_t *)handle);
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if (ret)
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return -ENOMEM;
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cgs_handle = *(cgs_handle_t *)handle;
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ret = cgs_gmap_gpu_mem(device, cgs_handle, mc_addr);
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if (ret)
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goto error_gmap;
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ret = cgs_kmap_gpu_mem(device, cgs_handle, kptr);
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if (ret)
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goto error_kmap;
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return 0;
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error_kmap:
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cgs_gunmap_gpu_mem(device, cgs_handle);
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error_gmap:
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cgs_free_gpu_mem(device, cgs_handle);
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return ret;
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}
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int smu_free_memory(void *device, void *handle)
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{
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cgs_handle_t cgs_handle = (cgs_handle_t)handle;
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if (device == NULL || handle == NULL)
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return -EINVAL;
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cgs_kunmap_gpu_mem(device, cgs_handle);
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cgs_gunmap_gpu_mem(device, cgs_handle);
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cgs_free_gpu_mem(device, cgs_handle);
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return 0;
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}
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int smum_init_smc_table(struct pp_hwmgr *hwmgr)
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{
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if (NULL != hwmgr->smumgr->smumgr_funcs->init_smc_table)
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return hwmgr->smumgr->smumgr_funcs->init_smc_table(hwmgr);
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return 0;
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}
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int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
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{
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if (NULL != hwmgr->smumgr->smumgr_funcs->populate_all_graphic_levels)
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return hwmgr->smumgr->smumgr_funcs->populate_all_graphic_levels(hwmgr);
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return 0;
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}
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int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
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{
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if (NULL != hwmgr->smumgr->smumgr_funcs->populate_all_memory_levels)
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return hwmgr->smumgr->smumgr_funcs->populate_all_memory_levels(hwmgr);
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return 0;
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}
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/*this interface is needed by island ci/vi */
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int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
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{
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if (NULL != hwmgr->smumgr->smumgr_funcs->initialize_mc_reg_table)
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return hwmgr->smumgr->smumgr_funcs->initialize_mc_reg_table(hwmgr);
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return 0;
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}
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bool smum_is_dpm_running(struct pp_hwmgr *hwmgr)
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{
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if (NULL != hwmgr->smumgr->smumgr_funcs->is_dpm_running)
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return hwmgr->smumgr->smumgr_funcs->is_dpm_running(hwmgr);
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return true;
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}
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