521 lines
14 KiB
C
521 lines
14 KiB
C
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/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <linux/console.h>
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#include <linux/vgaarb.h>
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#include <linux/vga_switcheroo.h>
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#include "i915_drv.h"
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#define GEN_DEFAULT_PIPEOFFSETS \
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.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
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PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
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.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
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TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
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.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
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#define GEN_CHV_PIPEOFFSETS \
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.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
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CHV_PIPE_C_OFFSET }, \
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.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
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CHV_TRANSCODER_C_OFFSET, }, \
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.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
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CHV_PALETTE_C_OFFSET }
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#define CURSOR_OFFSETS \
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.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
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#define IVB_CURSOR_OFFSETS \
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.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
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#define BDW_COLORS \
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.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
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#define CHV_COLORS \
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.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
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#define GEN2_FEATURES \
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.gen = 2, .num_pipes = 1, \
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.has_overlay = 1, .overlay_needs_physical = 1, \
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.has_gmch_display = 1, \
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.hws_needs_physical = 1, \
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.ring_mask = RENDER_RING, \
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GEN_DEFAULT_PIPEOFFSETS, \
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CURSOR_OFFSETS
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static const struct intel_device_info intel_i830_info = {
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GEN2_FEATURES,
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.is_mobile = 1, .cursor_needs_physical = 1,
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.num_pipes = 2, /* legal, last one wins */
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};
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static const struct intel_device_info intel_845g_info = {
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GEN2_FEATURES,
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};
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static const struct intel_device_info intel_i85x_info = {
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GEN2_FEATURES,
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.is_i85x = 1, .is_mobile = 1,
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.num_pipes = 2, /* legal, last one wins */
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.cursor_needs_physical = 1,
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.has_fbc = 1,
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};
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static const struct intel_device_info intel_i865g_info = {
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GEN2_FEATURES,
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};
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#define GEN3_FEATURES \
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.gen = 3, .num_pipes = 2, \
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.has_gmch_display = 1, \
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.ring_mask = RENDER_RING, \
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GEN_DEFAULT_PIPEOFFSETS, \
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CURSOR_OFFSETS
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static const struct intel_device_info intel_i915g_info = {
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GEN3_FEATURES,
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.is_i915g = 1, .cursor_needs_physical = 1,
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.has_overlay = 1, .overlay_needs_physical = 1,
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.hws_needs_physical = 1,
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};
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static const struct intel_device_info intel_i915gm_info = {
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GEN3_FEATURES,
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.is_mobile = 1,
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.cursor_needs_physical = 1,
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.has_overlay = 1, .overlay_needs_physical = 1,
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.supports_tv = 1,
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.has_fbc = 1,
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.hws_needs_physical = 1,
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};
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static const struct intel_device_info intel_i945g_info = {
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GEN3_FEATURES,
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.has_hotplug = 1, .cursor_needs_physical = 1,
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.has_overlay = 1, .overlay_needs_physical = 1,
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.hws_needs_physical = 1,
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};
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static const struct intel_device_info intel_i945gm_info = {
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GEN3_FEATURES,
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.is_i945gm = 1, .is_mobile = 1,
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.has_hotplug = 1, .cursor_needs_physical = 1,
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.has_overlay = 1, .overlay_needs_physical = 1,
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.supports_tv = 1,
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.has_fbc = 1,
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.hws_needs_physical = 1,
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};
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#define GEN4_FEATURES \
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.gen = 4, .num_pipes = 2, \
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.has_hotplug = 1, \
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.has_gmch_display = 1, \
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.ring_mask = RENDER_RING, \
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GEN_DEFAULT_PIPEOFFSETS, \
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CURSOR_OFFSETS
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static const struct intel_device_info intel_i965g_info = {
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GEN4_FEATURES,
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.is_broadwater = 1,
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.has_overlay = 1,
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.hws_needs_physical = 1,
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};
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static const struct intel_device_info intel_i965gm_info = {
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GEN4_FEATURES,
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.is_crestline = 1,
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.is_mobile = 1, .has_fbc = 1,
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.has_overlay = 1,
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.supports_tv = 1,
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.hws_needs_physical = 1,
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};
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static const struct intel_device_info intel_g33_info = {
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GEN3_FEATURES,
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.is_g33 = 1,
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.has_hotplug = 1,
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.has_overlay = 1,
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};
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static const struct intel_device_info intel_g45_info = {
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GEN4_FEATURES,
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.is_g4x = 1,
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.has_pipe_cxsr = 1,
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.ring_mask = RENDER_RING | BSD_RING,
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};
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static const struct intel_device_info intel_gm45_info = {
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GEN4_FEATURES,
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.is_g4x = 1,
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.is_mobile = 1, .has_fbc = 1,
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.has_pipe_cxsr = 1,
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.supports_tv = 1,
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.ring_mask = RENDER_RING | BSD_RING,
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};
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static const struct intel_device_info intel_pineview_info = {
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GEN3_FEATURES,
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.is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
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.has_hotplug = 1,
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.has_overlay = 1,
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};
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#define GEN5_FEATURES \
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.gen = 5, .num_pipes = 2, \
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.has_hotplug = 1, \
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.has_gmbus_irq = 1, \
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.ring_mask = RENDER_RING | BSD_RING, \
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GEN_DEFAULT_PIPEOFFSETS, \
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CURSOR_OFFSETS
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static const struct intel_device_info intel_ironlake_d_info = {
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GEN5_FEATURES,
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};
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static const struct intel_device_info intel_ironlake_m_info = {
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GEN5_FEATURES,
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.is_mobile = 1,
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};
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#define GEN6_FEATURES \
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.gen = 6, .num_pipes = 2, \
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.has_hotplug = 1, \
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.has_fbc = 1, \
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.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
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.has_llc = 1, \
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.has_rc6 = 1, \
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.has_rc6p = 1, \
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.has_gmbus_irq = 1, \
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.has_hw_contexts = 1, \
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GEN_DEFAULT_PIPEOFFSETS, \
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CURSOR_OFFSETS
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static const struct intel_device_info intel_sandybridge_d_info = {
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GEN6_FEATURES,
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};
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static const struct intel_device_info intel_sandybridge_m_info = {
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GEN6_FEATURES,
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.is_mobile = 1,
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};
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#define GEN7_FEATURES \
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.gen = 7, .num_pipes = 3, \
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.has_hotplug = 1, \
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.has_fbc = 1, \
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.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
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.has_llc = 1, \
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.has_rc6 = 1, \
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.has_rc6p = 1, \
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.has_gmbus_irq = 1, \
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.has_hw_contexts = 1, \
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GEN_DEFAULT_PIPEOFFSETS, \
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IVB_CURSOR_OFFSETS
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static const struct intel_device_info intel_ivybridge_d_info = {
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GEN7_FEATURES,
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.is_ivybridge = 1,
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.has_l3_dpf = 1,
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};
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static const struct intel_device_info intel_ivybridge_m_info = {
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GEN7_FEATURES,
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.is_ivybridge = 1,
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.is_mobile = 1,
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.has_l3_dpf = 1,
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};
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static const struct intel_device_info intel_ivybridge_q_info = {
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GEN7_FEATURES,
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.is_ivybridge = 1,
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.num_pipes = 0, /* legal, last one wins */
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.has_l3_dpf = 1,
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};
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#define VLV_FEATURES \
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.gen = 7, .num_pipes = 2, \
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.has_psr = 1, \
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.has_runtime_pm = 1, \
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.has_rc6 = 1, \
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.has_gmbus_irq = 1, \
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.has_hw_contexts = 1, \
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.has_gmch_display = 1, \
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.has_hotplug = 1, \
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.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
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.display_mmio_offset = VLV_DISPLAY_BASE, \
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GEN_DEFAULT_PIPEOFFSETS, \
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CURSOR_OFFSETS
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static const struct intel_device_info intel_valleyview_info = {
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VLV_FEATURES,
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.is_valleyview = 1,
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};
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#define HSW_FEATURES \
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GEN7_FEATURES, \
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.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
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.has_ddi = 1, \
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.has_fpga_dbg = 1, \
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.has_psr = 1, \
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.has_resource_streamer = 1, \
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.has_dp_mst = 1, \
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.has_rc6p = 0 /* RC6p removed-by HSW */, \
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.has_runtime_pm = 1
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static const struct intel_device_info intel_haswell_info = {
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HSW_FEATURES,
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.is_haswell = 1,
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.has_l3_dpf = 1,
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};
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#define BDW_FEATURES \
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HSW_FEATURES, \
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BDW_COLORS, \
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.has_logical_ring_contexts = 1
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static const struct intel_device_info intel_broadwell_info = {
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BDW_FEATURES,
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.gen = 8,
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.is_broadwell = 1,
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};
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static const struct intel_device_info intel_broadwell_gt3_info = {
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BDW_FEATURES,
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.gen = 8,
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.is_broadwell = 1,
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.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
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};
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static const struct intel_device_info intel_cherryview_info = {
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.gen = 8, .num_pipes = 3,
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.has_hotplug = 1,
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.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
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.is_cherryview = 1,
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.has_psr = 1,
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.has_runtime_pm = 1,
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.has_resource_streamer = 1,
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.has_rc6 = 1,
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.has_gmbus_irq = 1,
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.has_hw_contexts = 1,
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.has_logical_ring_contexts = 1,
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.has_gmch_display = 1,
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.display_mmio_offset = VLV_DISPLAY_BASE,
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GEN_CHV_PIPEOFFSETS,
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CURSOR_OFFSETS,
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CHV_COLORS,
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};
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static const struct intel_device_info intel_skylake_info = {
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BDW_FEATURES,
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.is_skylake = 1,
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.gen = 9,
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.has_csr = 1,
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.has_guc = 1,
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.ddb_size = 896,
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};
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static const struct intel_device_info intel_skylake_gt3_info = {
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BDW_FEATURES,
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.is_skylake = 1,
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.gen = 9,
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.has_csr = 1,
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.has_guc = 1,
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.ddb_size = 896,
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.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
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};
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static const struct intel_device_info intel_broxton_info = {
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.is_broxton = 1,
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.gen = 9,
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.has_hotplug = 1,
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.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
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.num_pipes = 3,
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.has_ddi = 1,
|
||
|
|
.has_fpga_dbg = 1,
|
||
|
|
.has_fbc = 1,
|
||
|
|
.has_runtime_pm = 1,
|
||
|
|
.has_pooled_eu = 0,
|
||
|
|
.has_csr = 1,
|
||
|
|
.has_resource_streamer = 1,
|
||
|
|
.has_rc6 = 1,
|
||
|
|
.has_dp_mst = 1,
|
||
|
|
.has_gmbus_irq = 1,
|
||
|
|
.has_hw_contexts = 1,
|
||
|
|
.has_logical_ring_contexts = 1,
|
||
|
|
.has_guc = 1,
|
||
|
|
.ddb_size = 512,
|
||
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
||
|
|
IVB_CURSOR_OFFSETS,
|
||
|
|
BDW_COLORS,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct intel_device_info intel_kabylake_info = {
|
||
|
|
BDW_FEATURES,
|
||
|
|
.is_kabylake = 1,
|
||
|
|
.gen = 9,
|
||
|
|
.has_csr = 1,
|
||
|
|
.has_guc = 1,
|
||
|
|
.ddb_size = 896,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct intel_device_info intel_kabylake_gt3_info = {
|
||
|
|
BDW_FEATURES,
|
||
|
|
.is_kabylake = 1,
|
||
|
|
.gen = 9,
|
||
|
|
.has_csr = 1,
|
||
|
|
.has_guc = 1,
|
||
|
|
.ddb_size = 896,
|
||
|
|
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Make sure any device matches here are from most specific to most
|
||
|
|
* general. For example, since the Quanta match is based on the subsystem
|
||
|
|
* and subvendor IDs, we need it to come before the more general IVB
|
||
|
|
* PCI ID matches, otherwise we'll use the wrong info struct above.
|
||
|
|
*/
|
||
|
|
static const struct pci_device_id pciidlist[] = {
|
||
|
|
INTEL_I830_IDS(&intel_i830_info),
|
||
|
|
INTEL_I845G_IDS(&intel_845g_info),
|
||
|
|
INTEL_I85X_IDS(&intel_i85x_info),
|
||
|
|
INTEL_I865G_IDS(&intel_i865g_info),
|
||
|
|
INTEL_I915G_IDS(&intel_i915g_info),
|
||
|
|
INTEL_I915GM_IDS(&intel_i915gm_info),
|
||
|
|
INTEL_I945G_IDS(&intel_i945g_info),
|
||
|
|
INTEL_I945GM_IDS(&intel_i945gm_info),
|
||
|
|
INTEL_I965G_IDS(&intel_i965g_info),
|
||
|
|
INTEL_G33_IDS(&intel_g33_info),
|
||
|
|
INTEL_I965GM_IDS(&intel_i965gm_info),
|
||
|
|
INTEL_GM45_IDS(&intel_gm45_info),
|
||
|
|
INTEL_G45_IDS(&intel_g45_info),
|
||
|
|
INTEL_PINEVIEW_IDS(&intel_pineview_info),
|
||
|
|
INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
|
||
|
|
INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
|
||
|
|
INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
|
||
|
|
INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
|
||
|
|
INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
|
||
|
|
INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
|
||
|
|
INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
|
||
|
|
INTEL_HSW_IDS(&intel_haswell_info),
|
||
|
|
INTEL_VLV_IDS(&intel_valleyview_info),
|
||
|
|
INTEL_BDW_GT12_IDS(&intel_broadwell_info),
|
||
|
|
INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
|
||
|
|
INTEL_BDW_RSVD_IDS(&intel_broadwell_info),
|
||
|
|
INTEL_CHV_IDS(&intel_cherryview_info),
|
||
|
|
INTEL_SKL_GT1_IDS(&intel_skylake_info),
|
||
|
|
INTEL_SKL_GT2_IDS(&intel_skylake_info),
|
||
|
|
INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
|
||
|
|
INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
|
||
|
|
INTEL_BXT_IDS(&intel_broxton_info),
|
||
|
|
INTEL_KBL_GT1_IDS(&intel_kabylake_info),
|
||
|
|
INTEL_KBL_GT2_IDS(&intel_kabylake_info),
|
||
|
|
INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
|
||
|
|
INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
|
||
|
|
{0, 0, 0}
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(pci, pciidlist);
|
||
|
|
|
||
|
|
static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||
|
|
{
|
||
|
|
struct intel_device_info *intel_info =
|
||
|
|
(struct intel_device_info *) ent->driver_data;
|
||
|
|
|
||
|
|
if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
|
||
|
|
DRM_INFO("This hardware requires preliminary hardware support.\n"
|
||
|
|
"See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
|
||
|
|
return -ENODEV;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Only bind to function 0 of the device. Early generations
|
||
|
|
* used function 1 as a placeholder for multi-head. This causes
|
||
|
|
* us confusion instead, especially on the systems where both
|
||
|
|
* functions have the same PCI-ID!
|
||
|
|
*/
|
||
|
|
if (PCI_FUNC(pdev->devfn))
|
||
|
|
return -ENODEV;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* apple-gmux is needed on dual GPU MacBook Pro
|
||
|
|
* to probe the panel if we're the inactive GPU.
|
||
|
|
*/
|
||
|
|
if (vga_switcheroo_client_probe_defer(pdev))
|
||
|
|
return -EPROBE_DEFER;
|
||
|
|
|
||
|
|
return i915_driver_load(pdev, ent);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void i915_pci_remove(struct pci_dev *pdev)
|
||
|
|
{
|
||
|
|
struct drm_device *dev = pci_get_drvdata(pdev);
|
||
|
|
|
||
|
|
i915_driver_unload(dev);
|
||
|
|
drm_dev_unref(dev);
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct pci_driver i915_pci_driver = {
|
||
|
|
.name = DRIVER_NAME,
|
||
|
|
.id_table = pciidlist,
|
||
|
|
.probe = i915_pci_probe,
|
||
|
|
.remove = i915_pci_remove,
|
||
|
|
.driver.pm = &i915_pm_ops,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init i915_init(void)
|
||
|
|
{
|
||
|
|
bool use_kms = true;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Enable KMS by default, unless explicitly overriden by
|
||
|
|
* either the i915.modeset prarameter or by the
|
||
|
|
* vga_text_mode_force boot option.
|
||
|
|
*/
|
||
|
|
|
||
|
|
if (i915.modeset == 0)
|
||
|
|
use_kms = false;
|
||
|
|
|
||
|
|
if (vgacon_text_force() && i915.modeset == -1)
|
||
|
|
use_kms = false;
|
||
|
|
|
||
|
|
if (!use_kms) {
|
||
|
|
/* Silently fail loading to not upset userspace. */
|
||
|
|
DRM_DEBUG_DRIVER("KMS disabled.\n");
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
return pci_register_driver(&i915_pci_driver);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void __exit i915_exit(void)
|
||
|
|
{
|
||
|
|
if (!i915_pci_driver.driver.owner)
|
||
|
|
return;
|
||
|
|
|
||
|
|
pci_unregister_driver(&i915_pci_driver);
|
||
|
|
}
|
||
|
|
|
||
|
|
module_init(i915_init);
|
||
|
|
module_exit(i915_exit);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Tungsten Graphics, Inc.");
|
||
|
|
MODULE_AUTHOR("Intel Corporation");
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
||
|
|
MODULE_LICENSE("GPL and additional rights");
|