543 lines
14 KiB
C
543 lines
14 KiB
C
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/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <linux/firmware.h>
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#include "i915_drv.h"
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#include "i915_reg.h"
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/**
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* DOC: csr support for dmc
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*
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* Display Context Save and Restore (CSR) firmware support added from gen9
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* onwards to drive newly added DMC (Display microcontroller) in display
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* engine to save and restore the state of display engine when it enter into
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* low-power state and comes back to normal.
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*/
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#define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"
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MODULE_FIRMWARE(I915_CSR_KBL);
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#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1)
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#define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin"
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MODULE_FIRMWARE(I915_CSR_SKL);
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#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 26)
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#define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin"
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MODULE_FIRMWARE(I915_CSR_BXT);
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#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
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#define FIRMWARE_URL "https://01.org/linuxgraphics/intel-linux-graphics-firmwares"
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#define CSR_MAX_FW_SIZE 0x2FFF
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#define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
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struct intel_css_header {
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/* 0x09 for DMC */
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uint32_t module_type;
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/* Includes the DMC specific header in dwords */
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uint32_t header_len;
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/* always value would be 0x10000 */
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uint32_t header_ver;
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/* Not used */
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uint32_t module_id;
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/* Not used */
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uint32_t module_vendor;
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/* in YYYYMMDD format */
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uint32_t date;
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/* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
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uint32_t size;
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/* Not used */
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uint32_t key_size;
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/* Not used */
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uint32_t modulus_size;
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/* Not used */
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uint32_t exponent_size;
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/* Not used */
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uint32_t reserved1[12];
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/* Major Minor */
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uint32_t version;
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/* Not used */
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uint32_t reserved2[8];
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/* Not used */
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uint32_t kernel_header_info;
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} __packed;
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struct intel_fw_info {
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uint16_t reserved1;
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/* Stepping (A, B, C, ..., *). * is a wildcard */
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char stepping;
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/* Sub-stepping (0, 1, ..., *). * is a wildcard */
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char substepping;
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uint32_t offset;
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uint32_t reserved2;
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} __packed;
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struct intel_package_header {
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/* DMC container header length in dwords */
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unsigned char header_len;
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/* always value would be 0x01 */
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unsigned char header_ver;
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unsigned char reserved[10];
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/* Number of valid entries in the FWInfo array below */
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uint32_t num_entries;
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struct intel_fw_info fw_info[20];
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} __packed;
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struct intel_dmc_header {
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/* always value would be 0x40403E3E */
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uint32_t signature;
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/* DMC binary header length */
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unsigned char header_len;
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/* 0x01 */
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unsigned char header_ver;
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/* Reserved */
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uint16_t dmcc_ver;
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/* Major, Minor */
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uint32_t project;
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/* Firmware program size (excluding header) in dwords */
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uint32_t fw_size;
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/* Major Minor version */
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uint32_t fw_version;
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/* Number of valid MMIO cycles present. */
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uint32_t mmio_count;
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/* MMIO address */
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uint32_t mmioaddr[8];
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/* MMIO data */
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uint32_t mmiodata[8];
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/* FW filename */
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unsigned char dfile[32];
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uint32_t reserved1[2];
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} __packed;
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struct stepping_info {
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char stepping;
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char substepping;
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};
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static const struct stepping_info kbl_stepping_info[] = {
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{'A', '0'}, {'B', '0'}, {'C', '0'},
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{'D', '0'}, {'E', '0'}, {'F', '0'},
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{'G', '0'}, {'H', '0'}, {'I', '0'},
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};
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static const struct stepping_info skl_stepping_info[] = {
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{'A', '0'}, {'B', '0'}, {'C', '0'},
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{'D', '0'}, {'E', '0'}, {'F', '0'},
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{'G', '0'}, {'H', '0'}, {'I', '0'},
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{'J', '0'}, {'K', '0'}
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};
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static const struct stepping_info bxt_stepping_info[] = {
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{'A', '0'}, {'A', '1'}, {'A', '2'},
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{'B', '0'}, {'B', '1'}, {'B', '2'}
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};
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static const struct stepping_info no_stepping_info = { '*', '*' };
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static const struct stepping_info *
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intel_get_stepping_info(struct drm_i915_private *dev_priv)
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{
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const struct stepping_info *si;
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unsigned int size;
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if (IS_KABYLAKE(dev_priv)) {
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size = ARRAY_SIZE(kbl_stepping_info);
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si = kbl_stepping_info;
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} else if (IS_SKYLAKE(dev_priv)) {
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size = ARRAY_SIZE(skl_stepping_info);
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si = skl_stepping_info;
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} else if (IS_BROXTON(dev_priv)) {
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size = ARRAY_SIZE(bxt_stepping_info);
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si = bxt_stepping_info;
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} else {
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size = 0;
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}
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if (INTEL_REVID(dev_priv) < size)
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return si + INTEL_REVID(dev_priv);
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return &no_stepping_info;
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}
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static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
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{
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uint32_t val, mask;
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mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
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if (IS_BROXTON(dev_priv))
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mask |= DC_STATE_DEBUG_MASK_CORES;
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/* The below bit doesn't need to be cleared ever afterwards */
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val = I915_READ(DC_STATE_DEBUG);
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if ((val & mask) != mask) {
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val |= mask;
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I915_WRITE(DC_STATE_DEBUG, val);
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POSTING_READ(DC_STATE_DEBUG);
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}
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}
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/**
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* intel_csr_load_program() - write the firmware from memory to register.
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* @dev_priv: i915 drm device.
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*
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* CSR firmware is read from a .bin file and kept in internal memory one time.
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* Everytime display comes back from low power state this function is called to
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* copy the firmware from internal memory to registers.
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*/
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void intel_csr_load_program(struct drm_i915_private *dev_priv)
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{
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u32 *payload = dev_priv->csr.dmc_payload;
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uint32_t i, fw_size;
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if (!IS_GEN9(dev_priv)) {
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DRM_ERROR("No CSR support available for this platform\n");
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return;
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}
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if (!dev_priv->csr.dmc_payload) {
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DRM_ERROR("Tried to program CSR with empty payload\n");
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return;
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}
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fw_size = dev_priv->csr.dmc_fw_size;
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for (i = 0; i < fw_size; i++)
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I915_WRITE(CSR_PROGRAM(i), payload[i]);
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for (i = 0; i < dev_priv->csr.mmio_count; i++) {
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I915_WRITE(dev_priv->csr.mmioaddr[i],
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dev_priv->csr.mmiodata[i]);
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}
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dev_priv->csr.dc_state = 0;
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gen9_set_dc_state_debugmask(dev_priv);
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}
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static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
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const struct firmware *fw)
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{
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struct intel_css_header *css_header;
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struct intel_package_header *package_header;
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struct intel_dmc_header *dmc_header;
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struct intel_csr *csr = &dev_priv->csr;
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const struct stepping_info *si = intel_get_stepping_info(dev_priv);
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uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
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uint32_t i;
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uint32_t *dmc_payload;
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uint32_t required_version;
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size_t fsize;
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if (!fw)
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return NULL;
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fsize = sizeof(struct intel_css_header) +
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sizeof(struct intel_package_header) +
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sizeof(struct intel_dmc_header);
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if (fsize > fw->size)
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goto error_truncated;
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/* Extract CSS Header information*/
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css_header = (struct intel_css_header *)fw->data;
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if (sizeof(struct intel_css_header) !=
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(css_header->header_len * 4)) {
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DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
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(css_header->header_len * 4));
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return NULL;
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}
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csr->version = css_header->version;
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if (IS_KABYLAKE(dev_priv)) {
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required_version = KBL_CSR_VERSION_REQUIRED;
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} else if (IS_SKYLAKE(dev_priv)) {
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required_version = SKL_CSR_VERSION_REQUIRED;
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} else if (IS_BROXTON(dev_priv)) {
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required_version = BXT_CSR_VERSION_REQUIRED;
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} else {
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MISSING_CASE(INTEL_REVID(dev_priv));
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required_version = 0;
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}
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if (csr->version != required_version) {
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DRM_INFO("Refusing to load DMC firmware v%u.%u,"
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" please use v%u.%u [" FIRMWARE_URL "].\n",
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CSR_VERSION_MAJOR(csr->version),
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CSR_VERSION_MINOR(csr->version),
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CSR_VERSION_MAJOR(required_version),
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CSR_VERSION_MINOR(required_version));
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return NULL;
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}
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readcount += sizeof(struct intel_css_header);
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/* Extract Package Header information*/
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package_header = (struct intel_package_header *)
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&fw->data[readcount];
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if (sizeof(struct intel_package_header) !=
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(package_header->header_len * 4)) {
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DRM_ERROR("Firmware has wrong package header length %u bytes\n",
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(package_header->header_len * 4));
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return NULL;
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}
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readcount += sizeof(struct intel_package_header);
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/* Search for dmc_offset to find firware binary. */
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for (i = 0; i < package_header->num_entries; i++) {
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if (package_header->fw_info[i].substepping == '*' &&
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si->stepping == package_header->fw_info[i].stepping) {
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dmc_offset = package_header->fw_info[i].offset;
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break;
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} else if (si->stepping == package_header->fw_info[i].stepping &&
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si->substepping == package_header->fw_info[i].substepping) {
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dmc_offset = package_header->fw_info[i].offset;
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break;
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} else if (package_header->fw_info[i].stepping == '*' &&
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package_header->fw_info[i].substepping == '*')
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dmc_offset = package_header->fw_info[i].offset;
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}
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if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
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DRM_ERROR("Firmware not supported for %c stepping\n",
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si->stepping);
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return NULL;
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}
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readcount += dmc_offset;
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fsize += dmc_offset;
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if (fsize > fw->size)
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goto error_truncated;
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/* Extract dmc_header information. */
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dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
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if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
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DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
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(dmc_header->header_len));
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return NULL;
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}
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readcount += sizeof(struct intel_dmc_header);
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/* Cache the dmc header info. */
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|
|
if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
|
||
|
|
DRM_ERROR("Firmware has wrong mmio count %u\n",
|
||
|
|
dmc_header->mmio_count);
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
csr->mmio_count = dmc_header->mmio_count;
|
||
|
|
for (i = 0; i < dmc_header->mmio_count; i++) {
|
||
|
|
if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
|
||
|
|
dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
|
||
|
|
DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
|
||
|
|
dmc_header->mmioaddr[i]);
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
|
||
|
|
csr->mmiodata[i] = dmc_header->mmiodata[i];
|
||
|
|
}
|
||
|
|
|
||
|
|
/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
|
||
|
|
nbytes = dmc_header->fw_size * 4;
|
||
|
|
fsize += nbytes;
|
||
|
|
if (fsize > fw->size)
|
||
|
|
goto error_truncated;
|
||
|
|
|
||
|
|
if (nbytes > CSR_MAX_FW_SIZE) {
|
||
|
|
DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
csr->dmc_fw_size = dmc_header->fw_size;
|
||
|
|
|
||
|
|
dmc_payload = kmalloc(nbytes, GFP_KERNEL);
|
||
|
|
if (!dmc_payload) {
|
||
|
|
DRM_ERROR("Memory allocation failed for dmc payload\n");
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
return memcpy(dmc_payload, &fw->data[readcount], nbytes);
|
||
|
|
|
||
|
|
error_truncated:
|
||
|
|
DRM_ERROR("Truncated DMC firmware, rejecting.\n");
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void csr_load_work_fn(struct work_struct *work)
|
||
|
|
{
|
||
|
|
struct drm_i915_private *dev_priv;
|
||
|
|
struct intel_csr *csr;
|
||
|
|
const struct firmware *fw;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
dev_priv = container_of(work, typeof(*dev_priv), csr.work);
|
||
|
|
csr = &dev_priv->csr;
|
||
|
|
|
||
|
|
ret = request_firmware(&fw, dev_priv->csr.fw_path,
|
||
|
|
&dev_priv->drm.pdev->dev);
|
||
|
|
if (fw)
|
||
|
|
dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
|
||
|
|
|
||
|
|
if (dev_priv->csr.dmc_payload) {
|
||
|
|
intel_csr_load_program(dev_priv);
|
||
|
|
|
||
|
|
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
|
||
|
|
|
||
|
|
DRM_INFO("Finished loading %s (v%u.%u)\n",
|
||
|
|
dev_priv->csr.fw_path,
|
||
|
|
CSR_VERSION_MAJOR(csr->version),
|
||
|
|
CSR_VERSION_MINOR(csr->version));
|
||
|
|
} else {
|
||
|
|
dev_notice(dev_priv->drm.dev,
|
||
|
|
"Failed to load DMC firmware"
|
||
|
|
" [" FIRMWARE_URL "],"
|
||
|
|
" disabling runtime power management.\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
release_firmware(fw);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* intel_csr_ucode_init() - initialize the firmware loading.
|
||
|
|
* @dev_priv: i915 drm device.
|
||
|
|
*
|
||
|
|
* This function is called at the time of loading the display driver to read
|
||
|
|
* firmware from a .bin file and copied into a internal memory.
|
||
|
|
*/
|
||
|
|
void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
|
||
|
|
{
|
||
|
|
struct intel_csr *csr = &dev_priv->csr;
|
||
|
|
|
||
|
|
INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
|
||
|
|
|
||
|
|
if (!HAS_CSR(dev_priv))
|
||
|
|
return;
|
||
|
|
|
||
|
|
if (IS_KABYLAKE(dev_priv))
|
||
|
|
csr->fw_path = I915_CSR_KBL;
|
||
|
|
else if (IS_SKYLAKE(dev_priv))
|
||
|
|
csr->fw_path = I915_CSR_SKL;
|
||
|
|
else if (IS_BROXTON(dev_priv))
|
||
|
|
csr->fw_path = I915_CSR_BXT;
|
||
|
|
else {
|
||
|
|
DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Obtain a runtime pm reference, until CSR is loaded,
|
||
|
|
* to avoid entering runtime-suspend.
|
||
|
|
*/
|
||
|
|
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
|
||
|
|
|
||
|
|
schedule_work(&dev_priv->csr.work);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
|
||
|
|
* @dev_priv: i915 drm device
|
||
|
|
*
|
||
|
|
* Prepare the DMC firmware before entering system suspend. This includes
|
||
|
|
* flushing pending work items and releasing any resources acquired during
|
||
|
|
* init.
|
||
|
|
*/
|
||
|
|
void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
|
||
|
|
{
|
||
|
|
if (!HAS_CSR(dev_priv))
|
||
|
|
return;
|
||
|
|
|
||
|
|
flush_work(&dev_priv->csr.work);
|
||
|
|
|
||
|
|
/* Drop the reference held in case DMC isn't loaded. */
|
||
|
|
if (!dev_priv->csr.dmc_payload)
|
||
|
|
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* intel_csr_ucode_resume() - init CSR firmware during system resume
|
||
|
|
* @dev_priv: i915 drm device
|
||
|
|
*
|
||
|
|
* Reinitialize the DMC firmware during system resume, reacquiring any
|
||
|
|
* resources released in intel_csr_ucode_suspend().
|
||
|
|
*/
|
||
|
|
void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
|
||
|
|
{
|
||
|
|
if (!HAS_CSR(dev_priv))
|
||
|
|
return;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Reacquire the reference to keep RPM disabled in case DMC isn't
|
||
|
|
* loaded.
|
||
|
|
*/
|
||
|
|
if (!dev_priv->csr.dmc_payload)
|
||
|
|
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* intel_csr_ucode_fini() - unload the CSR firmware.
|
||
|
|
* @dev_priv: i915 drm device.
|
||
|
|
*
|
||
|
|
* Firmmware unloading includes freeing the internal memory and reset the
|
||
|
|
* firmware loading status.
|
||
|
|
*/
|
||
|
|
void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
|
||
|
|
{
|
||
|
|
if (!HAS_CSR(dev_priv))
|
||
|
|
return;
|
||
|
|
|
||
|
|
intel_csr_ucode_suspend(dev_priv);
|
||
|
|
|
||
|
|
kfree(dev_priv->csr.dmc_payload);
|
||
|
|
}
|