451 lines
11 KiB
C
451 lines
11 KiB
C
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/*
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* Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA,
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* All Rights Reserved.
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* Copyright (c) 2009 VMware, Inc., Palo Alto, CA., USA,
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "nouveau_drv.h"
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#include "nouveau_ttm.h"
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#include "nouveau_gem.h"
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#include "drm_legacy.h"
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#include <core/tegra.h>
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static int
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nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
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{
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struct nouveau_drm *drm = nouveau_bdev(man->bdev);
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struct nvkm_fb *fb = nvxx_fb(&drm->device);
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man->priv = fb;
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return 0;
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}
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static int
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nouveau_vram_manager_fini(struct ttm_mem_type_manager *man)
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{
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man->priv = NULL;
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return 0;
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}
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static inline void
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nvkm_mem_node_cleanup(struct nvkm_mem *node)
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{
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if (node->vma[0].node) {
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nvkm_vm_unmap(&node->vma[0]);
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nvkm_vm_put(&node->vma[0]);
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}
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if (node->vma[1].node) {
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nvkm_vm_unmap(&node->vma[1]);
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nvkm_vm_put(&node->vma[1]);
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}
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}
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static void
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nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
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struct ttm_mem_reg *mem)
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{
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struct nouveau_drm *drm = nouveau_bdev(man->bdev);
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struct nvkm_ram *ram = nvxx_fb(&drm->device)->ram;
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nvkm_mem_node_cleanup(mem->mm_node);
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ram->func->put(ram, (struct nvkm_mem **)&mem->mm_node);
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}
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static int
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nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
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struct ttm_buffer_object *bo,
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const struct ttm_place *place,
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struct ttm_mem_reg *mem)
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{
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struct nouveau_drm *drm = nouveau_bdev(man->bdev);
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struct nvkm_ram *ram = nvxx_fb(&drm->device)->ram;
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struct nouveau_bo *nvbo = nouveau_bo(bo);
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struct nvkm_mem *node;
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u32 size_nc = 0;
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int ret;
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if (drm->device.info.ram_size == 0)
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return -ENOMEM;
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if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
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size_nc = 1 << nvbo->page_shift;
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ret = ram->func->get(ram, mem->num_pages << PAGE_SHIFT,
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mem->page_alignment << PAGE_SHIFT, size_nc,
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(nvbo->tile_flags >> 8) & 0x3ff, &node);
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if (ret) {
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mem->mm_node = NULL;
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return (ret == -ENOSPC) ? 0 : ret;
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}
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node->page_shift = nvbo->page_shift;
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mem->mm_node = node;
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mem->start = node->offset >> PAGE_SHIFT;
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return 0;
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}
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const struct ttm_mem_type_manager_func nouveau_vram_manager = {
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nouveau_vram_manager_init,
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nouveau_vram_manager_fini,
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nouveau_vram_manager_new,
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nouveau_vram_manager_del,
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};
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static int
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nouveau_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
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{
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return 0;
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}
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static int
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nouveau_gart_manager_fini(struct ttm_mem_type_manager *man)
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{
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return 0;
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}
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static void
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nouveau_gart_manager_del(struct ttm_mem_type_manager *man,
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struct ttm_mem_reg *mem)
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{
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nvkm_mem_node_cleanup(mem->mm_node);
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kfree(mem->mm_node);
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mem->mm_node = NULL;
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}
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static int
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nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
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struct ttm_buffer_object *bo,
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const struct ttm_place *place,
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struct ttm_mem_reg *mem)
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{
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struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
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struct nouveau_bo *nvbo = nouveau_bo(bo);
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struct nvkm_mem *node;
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node = kzalloc(sizeof(*node), GFP_KERNEL);
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if (!node)
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return -ENOMEM;
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node->page_shift = 12;
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switch (drm->device.info.family) {
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case NV_DEVICE_INFO_V0_TNT:
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case NV_DEVICE_INFO_V0_CELSIUS:
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case NV_DEVICE_INFO_V0_KELVIN:
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case NV_DEVICE_INFO_V0_RANKINE:
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case NV_DEVICE_INFO_V0_CURIE:
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break;
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case NV_DEVICE_INFO_V0_TESLA:
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if (drm->device.info.chipset != 0x50)
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node->memtype = (nvbo->tile_flags & 0x7f00) >> 8;
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break;
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case NV_DEVICE_INFO_V0_FERMI:
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case NV_DEVICE_INFO_V0_KEPLER:
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case NV_DEVICE_INFO_V0_MAXWELL:
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case NV_DEVICE_INFO_V0_PASCAL:
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node->memtype = (nvbo->tile_flags & 0xff00) >> 8;
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break;
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default:
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NV_WARN(drm, "%s: unhandled family type %x\n", __func__,
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drm->device.info.family);
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break;
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}
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mem->mm_node = node;
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mem->start = 0;
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return 0;
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}
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static void
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nouveau_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
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{
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}
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const struct ttm_mem_type_manager_func nouveau_gart_manager = {
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nouveau_gart_manager_init,
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nouveau_gart_manager_fini,
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nouveau_gart_manager_new,
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nouveau_gart_manager_del,
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nouveau_gart_manager_debug
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};
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/*XXX*/
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#include <subdev/mmu/nv04.h>
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static int
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nv04_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
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{
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struct nouveau_drm *drm = nouveau_bdev(man->bdev);
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struct nvkm_mmu *mmu = nvxx_mmu(&drm->device);
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struct nv04_mmu *priv = (void *)mmu;
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struct nvkm_vm *vm = NULL;
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nvkm_vm_ref(priv->vm, &vm, NULL);
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man->priv = vm;
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return 0;
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}
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static int
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nv04_gart_manager_fini(struct ttm_mem_type_manager *man)
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{
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struct nvkm_vm *vm = man->priv;
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nvkm_vm_ref(NULL, &vm, NULL);
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man->priv = NULL;
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return 0;
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}
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static void
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nv04_gart_manager_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem)
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{
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struct nvkm_mem *node = mem->mm_node;
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if (node->vma[0].node)
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nvkm_vm_put(&node->vma[0]);
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kfree(mem->mm_node);
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mem->mm_node = NULL;
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}
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static int
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nv04_gart_manager_new(struct ttm_mem_type_manager *man,
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struct ttm_buffer_object *bo,
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const struct ttm_place *place,
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struct ttm_mem_reg *mem)
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{
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struct nvkm_mem *node;
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int ret;
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node = kzalloc(sizeof(*node), GFP_KERNEL);
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if (!node)
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return -ENOMEM;
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node->page_shift = 12;
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ret = nvkm_vm_get(man->priv, mem->num_pages << 12, node->page_shift,
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NV_MEM_ACCESS_RW, &node->vma[0]);
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if (ret) {
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kfree(node);
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return ret;
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}
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mem->mm_node = node;
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mem->start = node->vma[0].offset >> PAGE_SHIFT;
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return 0;
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}
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static void
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nv04_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
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{
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}
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const struct ttm_mem_type_manager_func nv04_gart_manager = {
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nv04_gart_manager_init,
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nv04_gart_manager_fini,
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nv04_gart_manager_new,
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nv04_gart_manager_del,
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nv04_gart_manager_debug
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};
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int
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nouveau_ttm_mmap(struct file *filp, struct vm_area_struct *vma)
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{
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struct drm_file *file_priv = filp->private_data;
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struct nouveau_drm *drm = nouveau_drm(file_priv->minor->dev);
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if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
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return drm_legacy_mmap(filp, vma);
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return ttm_bo_mmap(filp, vma, &drm->ttm.bdev);
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}
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static int
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nouveau_ttm_mem_global_init(struct drm_global_reference *ref)
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{
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return ttm_mem_global_init(ref->object);
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}
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static void
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nouveau_ttm_mem_global_release(struct drm_global_reference *ref)
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{
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ttm_mem_global_release(ref->object);
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}
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int
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nouveau_ttm_global_init(struct nouveau_drm *drm)
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{
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struct drm_global_reference *global_ref;
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int ret;
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global_ref = &drm->ttm.mem_global_ref;
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global_ref->global_type = DRM_GLOBAL_TTM_MEM;
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global_ref->size = sizeof(struct ttm_mem_global);
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global_ref->init = &nouveau_ttm_mem_global_init;
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global_ref->release = &nouveau_ttm_mem_global_release;
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ret = drm_global_item_ref(global_ref);
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if (unlikely(ret != 0)) {
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DRM_ERROR("Failed setting up TTM memory accounting\n");
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drm->ttm.mem_global_ref.release = NULL;
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return ret;
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}
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drm->ttm.bo_global_ref.mem_glob = global_ref->object;
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global_ref = &drm->ttm.bo_global_ref.ref;
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global_ref->global_type = DRM_GLOBAL_TTM_BO;
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global_ref->size = sizeof(struct ttm_bo_global);
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global_ref->init = &ttm_bo_global_init;
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global_ref->release = &ttm_bo_global_release;
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ret = drm_global_item_ref(global_ref);
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if (unlikely(ret != 0)) {
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DRM_ERROR("Failed setting up TTM BO subsystem\n");
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drm_global_item_unref(&drm->ttm.mem_global_ref);
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drm->ttm.mem_global_ref.release = NULL;
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return ret;
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}
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return 0;
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}
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void
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nouveau_ttm_global_release(struct nouveau_drm *drm)
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{
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if (drm->ttm.mem_global_ref.release == NULL)
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return;
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drm_global_item_unref(&drm->ttm.bo_global_ref.ref);
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drm_global_item_unref(&drm->ttm.mem_global_ref);
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drm->ttm.mem_global_ref.release = NULL;
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}
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int
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nouveau_ttm_init(struct nouveau_drm *drm)
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{
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struct nvkm_device *device = nvxx_device(&drm->device);
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struct nvkm_pci *pci = device->pci;
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struct drm_device *dev = drm->dev;
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u8 bits;
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int ret;
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if (pci && pci->agp.bridge) {
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drm->agp.bridge = pci->agp.bridge;
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drm->agp.base = pci->agp.base;
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drm->agp.size = pci->agp.size;
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drm->agp.cma = pci->agp.cma;
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}
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bits = nvxx_mmu(&drm->device)->dma_bits;
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if (nvxx_device(&drm->device)->func->pci) {
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if (drm->agp.bridge)
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bits = 32;
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} else if (device->func->tegra) {
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struct nvkm_device_tegra *tegra = device->func->tegra(device);
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/*
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* If the platform can use a IOMMU, then the addressable DMA
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* space is constrained by the IOMMU bit
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*/
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if (tegra->func->iommu_bit)
|
||
|
|
bits = min(bits, tegra->func->iommu_bit);
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = dma_set_mask(dev->dev, DMA_BIT_MASK(bits));
|
||
|
|
if (ret && bits != 32) {
|
||
|
|
bits = 32;
|
||
|
|
ret = dma_set_mask(dev->dev, DMA_BIT_MASK(bits));
|
||
|
|
}
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
ret = dma_set_coherent_mask(dev->dev, DMA_BIT_MASK(bits));
|
||
|
|
if (ret)
|
||
|
|
dma_set_coherent_mask(dev->dev, DMA_BIT_MASK(32));
|
||
|
|
|
||
|
|
ret = nouveau_ttm_global_init(drm);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
ret = ttm_bo_device_init(&drm->ttm.bdev,
|
||
|
|
drm->ttm.bo_global_ref.ref.object,
|
||
|
|
&nouveau_bo_driver,
|
||
|
|
dev->anon_inode->i_mapping,
|
||
|
|
DRM_FILE_PAGE_OFFSET,
|
||
|
|
bits <= 32 ? true : false);
|
||
|
|
if (ret) {
|
||
|
|
NV_ERROR(drm, "error initialising bo driver, %d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* VRAM init */
|
||
|
|
drm->gem.vram_available = drm->device.info.ram_user;
|
||
|
|
|
||
|
|
arch_io_reserve_memtype_wc(device->func->resource_addr(device, 1),
|
||
|
|
device->func->resource_size(device, 1));
|
||
|
|
|
||
|
|
ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_VRAM,
|
||
|
|
drm->gem.vram_available >> PAGE_SHIFT);
|
||
|
|
if (ret) {
|
||
|
|
NV_ERROR(drm, "VRAM mm init failed, %d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
drm->ttm.mtrr = arch_phys_wc_add(device->func->resource_addr(device, 1),
|
||
|
|
device->func->resource_size(device, 1));
|
||
|
|
|
||
|
|
/* GART init */
|
||
|
|
if (!drm->agp.bridge) {
|
||
|
|
drm->gem.gart_available = nvxx_mmu(&drm->device)->limit;
|
||
|
|
} else {
|
||
|
|
drm->gem.gart_available = drm->agp.size;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_TT,
|
||
|
|
drm->gem.gart_available >> PAGE_SHIFT);
|
||
|
|
if (ret) {
|
||
|
|
NV_ERROR(drm, "GART mm init failed, %d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
NV_INFO(drm, "VRAM: %d MiB\n", (u32)(drm->gem.vram_available >> 20));
|
||
|
|
NV_INFO(drm, "GART: %d MiB\n", (u32)(drm->gem.gart_available >> 20));
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
nouveau_ttm_fini(struct nouveau_drm *drm)
|
||
|
|
{
|
||
|
|
struct nvkm_device *device = nvxx_device(&drm->device);
|
||
|
|
|
||
|
|
ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_VRAM);
|
||
|
|
ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_TT);
|
||
|
|
|
||
|
|
ttm_bo_device_release(&drm->ttm.bdev);
|
||
|
|
|
||
|
|
nouveau_ttm_global_release(drm);
|
||
|
|
|
||
|
|
arch_phys_wc_del(drm->ttm.mtrr);
|
||
|
|
drm->ttm.mtrr = 0;
|
||
|
|
arch_io_free_memtype_wc(device->func->resource_addr(device, 1),
|
||
|
|
device->func->resource_size(device, 1));
|
||
|
|
|
||
|
|
}
|