233 lines
7.8 KiB
C
233 lines
7.8 KiB
C
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/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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* Copyright 2014 Rafał Miłecki
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <linux/hdmi.h>
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#include <drm/drmP.h>
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "radeon_audio.h"
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#include "r600d.h"
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void dce3_2_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
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u8 *sadb, int sad_count)
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{
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struct radeon_device *rdev = encoder->dev->dev_private;
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u32 tmp;
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/* program the speaker allocation */
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tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
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tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
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/* set HDMI mode */
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tmp |= HDMI_CONNECTION;
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if (sad_count)
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tmp |= SPEAKER_ALLOCATION(sadb[0]);
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else
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tmp |= SPEAKER_ALLOCATION(5); /* stereo */
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WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
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}
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void dce3_2_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
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u8 *sadb, int sad_count)
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{
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struct radeon_device *rdev = encoder->dev->dev_private;
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u32 tmp;
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/* program the speaker allocation */
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tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
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tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
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/* set DP mode */
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tmp |= DP_CONNECTION;
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if (sad_count)
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tmp |= SPEAKER_ALLOCATION(sadb[0]);
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else
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tmp |= SPEAKER_ALLOCATION(5); /* stereo */
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WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
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}
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void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder,
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struct cea_sad *sads, int sad_count)
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{
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int i;
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struct radeon_device *rdev = encoder->dev->dev_private;
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static const u16 eld_reg_to_type[][2] = {
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
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};
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for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
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u32 value = 0;
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u8 stereo_freqs = 0;
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int max_channels = -1;
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int j;
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for (j = 0; j < sad_count; j++) {
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struct cea_sad *sad = &sads[j];
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if (sad->format == eld_reg_to_type[i][1]) {
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if (sad->channels > max_channels) {
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value = MAX_CHANNELS(sad->channels) |
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DESCRIPTOR_BYTE_2(sad->byte2) |
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SUPPORTED_FREQUENCIES(sad->freq);
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max_channels = sad->channels;
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}
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if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
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stereo_freqs |= sad->freq;
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else
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break;
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}
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}
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value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
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WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
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}
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}
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void dce3_2_audio_set_dto(struct radeon_device *rdev,
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struct radeon_crtc *crtc, unsigned int clock)
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{
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struct radeon_encoder *radeon_encoder;
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struct radeon_encoder_atom_dig *dig;
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unsigned int max_ratio = clock / 24000;
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u32 dto_phase;
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u32 wallclock_ratio;
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u32 dto_cntl;
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if (!crtc)
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return;
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radeon_encoder = to_radeon_encoder(crtc->encoder);
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dig = radeon_encoder->enc_priv;
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if (!dig)
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return;
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if (max_ratio >= 8) {
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dto_phase = 192 * 1000;
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wallclock_ratio = 3;
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} else if (max_ratio >= 4) {
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dto_phase = 96 * 1000;
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wallclock_ratio = 2;
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} else if (max_ratio >= 2) {
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dto_phase = 48 * 1000;
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wallclock_ratio = 1;
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} else {
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dto_phase = 24 * 1000;
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wallclock_ratio = 0;
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}
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/* Express [24MHz / target pixel clock] as an exact rational
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* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
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* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
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*/
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if (dig->dig_encoder == 0) {
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dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
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dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
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WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
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WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
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WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
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WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
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} else {
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dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
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dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
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WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);
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WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);
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WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
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WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
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}
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}
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void dce3_2_hdmi_update_acr(struct drm_encoder *encoder, long offset,
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const struct radeon_hdmi_acr *acr)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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WREG32(DCE3_HDMI0_ACR_PACKET_CONTROL + offset,
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HDMI0_ACR_SOURCE | /* select SW CTS value */
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HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
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WREG32_P(HDMI0_ACR_32_0 + offset,
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HDMI0_ACR_CTS_32(acr->cts_32khz),
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~HDMI0_ACR_CTS_32_MASK);
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WREG32_P(HDMI0_ACR_32_1 + offset,
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HDMI0_ACR_N_32(acr->n_32khz),
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~HDMI0_ACR_N_32_MASK);
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WREG32_P(HDMI0_ACR_44_0 + offset,
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HDMI0_ACR_CTS_44(acr->cts_44_1khz),
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~HDMI0_ACR_CTS_44_MASK);
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WREG32_P(HDMI0_ACR_44_1 + offset,
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HDMI0_ACR_N_44(acr->n_44_1khz),
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~HDMI0_ACR_N_44_MASK);
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WREG32_P(HDMI0_ACR_48_0 + offset,
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HDMI0_ACR_CTS_48(acr->cts_48khz),
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~HDMI0_ACR_CTS_48_MASK);
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WREG32_P(HDMI0_ACR_48_1 + offset,
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HDMI0_ACR_N_48(acr->n_48khz),
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~HDMI0_ACR_N_48_MASK);
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}
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void dce3_2_set_audio_packet(struct drm_encoder *encoder, u32 offset)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
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HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
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HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
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WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
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AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
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AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
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WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
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HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
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HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */
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WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset,
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HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
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}
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void dce3_2_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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if (mute)
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WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE);
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else
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WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE);
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}
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