314 lines
8.2 KiB
C
314 lines
8.2 KiB
C
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/**************************************************************************
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*
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* Copyright © 2009-2015 VMware, Inc., Palo Alto, CA., USA
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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**************************************************************************/
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#include <drm/drmP.h>
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#include "vmwgfx_drv.h"
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#define VMW_FENCE_WRAP (1 << 24)
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irqreturn_t vmw_irq_handler(int irq, void *arg)
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{
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struct drm_device *dev = (struct drm_device *)arg;
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struct vmw_private *dev_priv = vmw_priv(dev);
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uint32_t status, masked_status;
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status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
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masked_status = status & READ_ONCE(dev_priv->irq_mask);
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if (likely(status))
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outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
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if (!status)
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return IRQ_NONE;
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if (masked_status & (SVGA_IRQFLAG_ANY_FENCE |
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SVGA_IRQFLAG_FENCE_GOAL)) {
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vmw_fences_update(dev_priv->fman);
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wake_up_all(&dev_priv->fence_queue);
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}
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if (masked_status & SVGA_IRQFLAG_FIFO_PROGRESS)
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wake_up_all(&dev_priv->fifo_queue);
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if (masked_status & (SVGA_IRQFLAG_COMMAND_BUFFER |
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SVGA_IRQFLAG_ERROR))
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vmw_cmdbuf_tasklet_schedule(dev_priv->cman);
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return IRQ_HANDLED;
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}
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static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t seqno)
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{
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return (vmw_read(dev_priv, SVGA_REG_BUSY) == 0);
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}
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void vmw_update_seqno(struct vmw_private *dev_priv,
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struct vmw_fifo_state *fifo_state)
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{
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u32 *fifo_mem = dev_priv->mmio_virt;
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uint32_t seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE);
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if (dev_priv->last_read_seqno != seqno) {
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dev_priv->last_read_seqno = seqno;
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vmw_marker_pull(&fifo_state->marker_queue, seqno);
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vmw_fences_update(dev_priv->fman);
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}
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}
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bool vmw_seqno_passed(struct vmw_private *dev_priv,
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uint32_t seqno)
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{
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struct vmw_fifo_state *fifo_state;
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bool ret;
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if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
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return true;
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fifo_state = &dev_priv->fifo;
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vmw_update_seqno(dev_priv, fifo_state);
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if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
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return true;
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if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE) &&
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vmw_fifo_idle(dev_priv, seqno))
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return true;
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/**
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* Then check if the seqno is higher than what we've actually
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* emitted. Then the fence is stale and signaled.
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*/
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ret = ((atomic_read(&dev_priv->marker_seq) - seqno)
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> VMW_FENCE_WRAP);
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return ret;
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}
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int vmw_fallback_wait(struct vmw_private *dev_priv,
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bool lazy,
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bool fifo_idle,
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uint32_t seqno,
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bool interruptible,
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unsigned long timeout)
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{
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struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
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uint32_t count = 0;
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uint32_t signal_seq;
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int ret;
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unsigned long end_jiffies = jiffies + timeout;
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bool (*wait_condition)(struct vmw_private *, uint32_t);
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DEFINE_WAIT(__wait);
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wait_condition = (fifo_idle) ? &vmw_fifo_idle :
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&vmw_seqno_passed;
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/**
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* Block command submission while waiting for idle.
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*/
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if (fifo_idle) {
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down_read(&fifo_state->rwsem);
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if (dev_priv->cman) {
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ret = vmw_cmdbuf_idle(dev_priv->cman, interruptible,
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10*HZ);
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if (ret)
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goto out_err;
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}
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}
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signal_seq = atomic_read(&dev_priv->marker_seq);
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ret = 0;
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for (;;) {
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prepare_to_wait(&dev_priv->fence_queue, &__wait,
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(interruptible) ?
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TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
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if (wait_condition(dev_priv, seqno))
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break;
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if (time_after_eq(jiffies, end_jiffies)) {
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DRM_ERROR("SVGA device lockup.\n");
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break;
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}
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if (lazy)
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schedule_timeout(1);
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else if ((++count & 0x0F) == 0) {
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/**
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* FIXME: Use schedule_hr_timeout here for
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* newer kernels and lower CPU utilization.
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*/
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__set_current_state(TASK_RUNNING);
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schedule();
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__set_current_state((interruptible) ?
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TASK_INTERRUPTIBLE :
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TASK_UNINTERRUPTIBLE);
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}
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if (interruptible && signal_pending(current)) {
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ret = -ERESTARTSYS;
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break;
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}
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}
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finish_wait(&dev_priv->fence_queue, &__wait);
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if (ret == 0 && fifo_idle) {
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u32 *fifo_mem = dev_priv->mmio_virt;
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vmw_mmio_write(signal_seq, fifo_mem + SVGA_FIFO_FENCE);
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}
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wake_up_all(&dev_priv->fence_queue);
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out_err:
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if (fifo_idle)
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up_read(&fifo_state->rwsem);
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return ret;
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}
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void vmw_generic_waiter_add(struct vmw_private *dev_priv,
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u32 flag, int *waiter_count)
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{
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spin_lock_bh(&dev_priv->waiter_lock);
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if ((*waiter_count)++ == 0) {
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outl(flag, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
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dev_priv->irq_mask |= flag;
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vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
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}
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spin_unlock_bh(&dev_priv->waiter_lock);
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}
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void vmw_generic_waiter_remove(struct vmw_private *dev_priv,
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u32 flag, int *waiter_count)
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{
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spin_lock_bh(&dev_priv->waiter_lock);
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if (--(*waiter_count) == 0) {
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dev_priv->irq_mask &= ~flag;
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vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
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}
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spin_unlock_bh(&dev_priv->waiter_lock);
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}
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void vmw_seqno_waiter_add(struct vmw_private *dev_priv)
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{
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vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_ANY_FENCE,
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&dev_priv->fence_queue_waiters);
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}
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void vmw_seqno_waiter_remove(struct vmw_private *dev_priv)
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{
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vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_ANY_FENCE,
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&dev_priv->fence_queue_waiters);
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}
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void vmw_goal_waiter_add(struct vmw_private *dev_priv)
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{
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vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_FENCE_GOAL,
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&dev_priv->goal_queue_waiters);
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}
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void vmw_goal_waiter_remove(struct vmw_private *dev_priv)
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{
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vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_FENCE_GOAL,
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&dev_priv->goal_queue_waiters);
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}
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int vmw_wait_seqno(struct vmw_private *dev_priv,
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bool lazy, uint32_t seqno,
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bool interruptible, unsigned long timeout)
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{
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long ret;
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struct vmw_fifo_state *fifo = &dev_priv->fifo;
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if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
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return 0;
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if (likely(vmw_seqno_passed(dev_priv, seqno)))
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return 0;
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vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
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if (!(fifo->capabilities & SVGA_FIFO_CAP_FENCE))
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return vmw_fallback_wait(dev_priv, lazy, true, seqno,
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interruptible, timeout);
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if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
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return vmw_fallback_wait(dev_priv, lazy, false, seqno,
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interruptible, timeout);
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vmw_seqno_waiter_add(dev_priv);
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if (interruptible)
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ret = wait_event_interruptible_timeout
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(dev_priv->fence_queue,
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vmw_seqno_passed(dev_priv, seqno),
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timeout);
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else
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ret = wait_event_timeout
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(dev_priv->fence_queue,
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vmw_seqno_passed(dev_priv, seqno),
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timeout);
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vmw_seqno_waiter_remove(dev_priv);
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if (unlikely(ret == 0))
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ret = -EBUSY;
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else if (likely(ret > 0))
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ret = 0;
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return ret;
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}
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void vmw_irq_preinstall(struct drm_device *dev)
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{
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struct vmw_private *dev_priv = vmw_priv(dev);
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uint32_t status;
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if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
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return;
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status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
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outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
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}
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int vmw_irq_postinstall(struct drm_device *dev)
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{
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return 0;
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}
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void vmw_irq_uninstall(struct drm_device *dev)
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{
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struct vmw_private *dev_priv = vmw_priv(dev);
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uint32_t status;
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if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
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return;
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vmw_write(dev_priv, SVGA_REG_IRQMASK, 0);
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status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
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outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
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}
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