221 lines
7.1 KiB
C
221 lines
7.1 KiB
C
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/*
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* ISH registers definitions
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*
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* Copyright (c) 2012-2016, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ISHTP_ISH_REGS_H_
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#define _ISHTP_ISH_REGS_H_
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/*** IPC PCI Offsets and sizes ***/
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/* ISH IPC Base Address */
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#define IPC_REG_BASE 0x0000
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/* Peripheral Interrupt Status Register */
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#define IPC_REG_PISR_CHV_AB (IPC_REG_BASE + 0x00)
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/* Peripheral Interrupt Mask Register */
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#define IPC_REG_PIMR_CHV_AB (IPC_REG_BASE + 0x04)
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/*BXT, CHV_K0*/
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/*Peripheral Interrupt Status Register */
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#define IPC_REG_PISR_BXT (IPC_REG_BASE + 0x0C)
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/*Peripheral Interrupt Mask Register */
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#define IPC_REG_PIMR_BXT (IPC_REG_BASE + 0x08)
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/***********************************/
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/* ISH Host Firmware status Register */
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#define IPC_REG_ISH_HOST_FWSTS (IPC_REG_BASE + 0x34)
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/* Host Communication Register */
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#define IPC_REG_HOST_COMM (IPC_REG_BASE + 0x38)
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/* Reset register */
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#define IPC_REG_ISH_RST (IPC_REG_BASE + 0x44)
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/* Inbound doorbell register Host to ISH */
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#define IPC_REG_HOST2ISH_DRBL (IPC_REG_BASE + 0x48)
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/* Outbound doorbell register ISH to Host */
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#define IPC_REG_ISH2HOST_DRBL (IPC_REG_BASE + 0x54)
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/* ISH to HOST message registers */
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#define IPC_REG_ISH2HOST_MSG (IPC_REG_BASE + 0x60)
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/* HOST to ISH message registers */
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#define IPC_REG_HOST2ISH_MSG (IPC_REG_BASE + 0xE0)
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/* REMAP2 to enable DMA (D3 RCR) */
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#define IPC_REG_ISH_RMP2 (IPC_REG_BASE + 0x368)
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#define IPC_REG_MAX (IPC_REG_BASE + 0x400)
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/*** register bits - HISR ***/
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/* bit corresponds HOST2ISH interrupt in PISR and PIMR registers */
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#define IPC_INT_HOST2ISH_BIT (1<<0)
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/***********************************/
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/*CHV_A0, CHV_B0*/
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/* bit corresponds ISH2HOST interrupt in PISR and PIMR registers */
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#define IPC_INT_ISH2HOST_BIT_CHV_AB (1<<3)
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/*BXT, CHV_K0*/
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/* bit corresponds ISH2HOST interrupt in PISR and PIMR registers */
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#define IPC_INT_ISH2HOST_BIT_BXT (1<<0)
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/***********************************/
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/* bit corresponds ISH2HOST busy clear interrupt in PIMR register */
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#define IPC_INT_ISH2HOST_CLR_MASK_BIT (1<<11)
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/* offset of ISH2HOST busy clear interrupt in IPC_BUSY_CLR register */
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#define IPC_INT_ISH2HOST_CLR_OFFS (0)
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/* bit corresponds ISH2HOST busy clear interrupt in IPC_BUSY_CLR register */
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#define IPC_INT_ISH2HOST_CLR_BIT (1<<IPC_INT_ISH2HOST_CLR_OFFS)
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/* bit corresponds busy bit in doorbell registers */
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#define IPC_DRBL_BUSY_OFFS (31)
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#define IPC_DRBL_BUSY_BIT (1<<IPC_DRBL_BUSY_OFFS)
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#define IPC_HOST_OWNS_MSG_OFFS (30)
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/*
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* A0: bit means that host owns MSGnn registers and is reading them.
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* ISH FW may not write to them
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*/
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#define IPC_HOST_OWNS_MSG_BIT (1<<IPC_HOST_OWNS_MSG_OFFS)
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/*
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* Host status bits (HOSTCOMM)
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*/
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/* bit corresponds host ready bit in Host Status Register (HOST_COMM) */
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#define IPC_HOSTCOMM_READY_OFFS (7)
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#define IPC_HOSTCOMM_READY_BIT (1<<IPC_HOSTCOMM_READY_OFFS)
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/***********************************/
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/*CHV_A0, CHV_B0*/
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#define IPC_HOSTCOMM_INT_EN_OFFS_CHV_AB (31)
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#define IPC_HOSTCOMM_INT_EN_BIT_CHV_AB \
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(1<<IPC_HOSTCOMM_INT_EN_OFFS_CHV_AB)
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/*BXT, CHV_K0*/
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#define IPC_PIMR_INT_EN_OFFS_BXT (0)
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#define IPC_PIMR_INT_EN_BIT_BXT (1<<IPC_PIMR_INT_EN_OFFS_BXT)
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#define IPC_HOST2ISH_BUSYCLEAR_MASK_OFFS_BXT (8)
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#define IPC_HOST2ISH_BUSYCLEAR_MASK_BIT \
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(1<<IPC_HOST2ISH_BUSYCLEAR_MASK_OFFS_BXT)
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/***********************************/
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/*
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* both Host and ISH have ILUP at bit 0
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* bit corresponds host ready bit in both status registers
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*/
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#define IPC_ILUP_OFFS (0)
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#define IPC_ILUP_BIT (1<<IPC_ILUP_OFFS)
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/*
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* FW status bits (relevant)
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*/
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#define IPC_FWSTS_ILUP 0x1
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#define IPC_FWSTS_ISHTP_UP (1<<1)
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#define IPC_FWSTS_DMA0 (1<<16)
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#define IPC_FWSTS_DMA1 (1<<17)
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#define IPC_FWSTS_DMA2 (1<<18)
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#define IPC_FWSTS_DMA3 (1<<19)
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#define IPC_ISH_IN_DMA \
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(IPC_FWSTS_DMA0 | IPC_FWSTS_DMA1 | IPC_FWSTS_DMA2 | IPC_FWSTS_DMA3)
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/* bit corresponds host ready bit in ISH FW Status Register */
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#define IPC_ISH_ISHTP_READY_OFFS (1)
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#define IPC_ISH_ISHTP_READY_BIT (1<<IPC_ISH_ISHTP_READY_OFFS)
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#define IPC_RMP2_DMA_ENABLED 0x1 /* Value to enable DMA, per D3 RCR */
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#define IPC_MSG_MAX_SIZE 0x80
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#define IPC_HEADER_LENGTH_MASK 0x03FF
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#define IPC_HEADER_PROTOCOL_MASK 0x0F
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#define IPC_HEADER_MNG_CMD_MASK 0x0F
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#define IPC_HEADER_LENGTH_OFFSET 0
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#define IPC_HEADER_PROTOCOL_OFFSET 10
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#define IPC_HEADER_MNG_CMD_OFFSET 16
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#define IPC_HEADER_GET_LENGTH(drbl_reg) \
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(((drbl_reg) >> IPC_HEADER_LENGTH_OFFSET)&IPC_HEADER_LENGTH_MASK)
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#define IPC_HEADER_GET_PROTOCOL(drbl_reg) \
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(((drbl_reg) >> IPC_HEADER_PROTOCOL_OFFSET)&IPC_HEADER_PROTOCOL_MASK)
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#define IPC_HEADER_GET_MNG_CMD(drbl_reg) \
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(((drbl_reg) >> IPC_HEADER_MNG_CMD_OFFSET)&IPC_HEADER_MNG_CMD_MASK)
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#define IPC_IS_BUSY(drbl_reg) \
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(((drbl_reg)&IPC_DRBL_BUSY_BIT) == ((uint32_t)IPC_DRBL_BUSY_BIT))
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/***********************************/
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/*CHV_A0, CHV_B0*/
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#define IPC_INT_FROM_ISH_TO_HOST_CHV_AB(drbl_reg) \
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(((drbl_reg)&IPC_INT_ISH2HOST_BIT_CHV_AB) == \
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((u32)IPC_INT_ISH2HOST_BIT_CHV_AB))
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/*BXT, CHV_K0*/
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#define IPC_INT_FROM_ISH_TO_HOST_BXT(drbl_reg) \
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(((drbl_reg)&IPC_INT_ISH2HOST_BIT_BXT) == \
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((u32)IPC_INT_ISH2HOST_BIT_BXT))
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/***********************************/
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#define IPC_BUILD_HEADER(length, protocol, busy) \
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(((busy)<<IPC_DRBL_BUSY_OFFS) | \
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((protocol) << IPC_HEADER_PROTOCOL_OFFSET) | \
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((length)<<IPC_HEADER_LENGTH_OFFSET))
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#define IPC_BUILD_MNG_MSG(cmd, length) \
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(((1)<<IPC_DRBL_BUSY_OFFS)| \
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((IPC_PROTOCOL_MNG)<<IPC_HEADER_PROTOCOL_OFFSET)| \
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((cmd)<<IPC_HEADER_MNG_CMD_OFFSET)| \
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((length)<<IPC_HEADER_LENGTH_OFFSET))
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#define IPC_SET_HOST_READY(host_status) \
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((host_status) |= (IPC_HOSTCOMM_READY_BIT))
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#define IPC_SET_HOST_ILUP(host_status) \
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((host_status) |= (IPC_ILUP_BIT))
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#define IPC_CLEAR_HOST_READY(host_status) \
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((host_status) ^= (IPC_HOSTCOMM_READY_BIT))
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#define IPC_CLEAR_HOST_ILUP(host_status) \
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((host_status) ^= (IPC_ILUP_BIT))
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/* todo - temp until PIMR HW ready */
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#define IPC_HOST_BUSY_READING_OFFS 6
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/* bit corresponds host ready bit in Host Status Register (HOST_COMM) */
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#define IPC_HOST_BUSY_READING_BIT (1<<IPC_HOST_BUSY_READING_OFFS)
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#define IPC_SET_HOST_BUSY_READING(host_status) \
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((host_status) |= (IPC_HOST_BUSY_READING_BIT))
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#define IPC_CLEAR_HOST_BUSY_READING(host_status)\
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((host_status) ^= (IPC_HOST_BUSY_READING_BIT))
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#define IPC_IS_ISH_ISHTP_READY(ish_status) \
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(((ish_status) & IPC_ISH_ISHTP_READY_BIT) == \
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((uint32_t)IPC_ISH_ISHTP_READY_BIT))
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#define IPC_IS_ISH_ILUP(ish_status) \
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(((ish_status) & IPC_ILUP_BIT) == ((uint32_t)IPC_ILUP_BIT))
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#define IPC_PROTOCOL_ISHTP 1
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#define IPC_PROTOCOL_MNG 3
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#define MNG_RX_CMPL_ENABLE 0
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#define MNG_RX_CMPL_DISABLE 1
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#define MNG_RX_CMPL_INDICATION 2
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#define MNG_RESET_NOTIFY 3
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#define MNG_RESET_NOTIFY_ACK 4
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#define MNG_SYNC_FW_CLOCK 5
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#define MNG_ILLEGAL_CMD 0xFF
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#endif /* _ISHTP_ISH_REGS_H_ */
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