287 lines
7.1 KiB
C
287 lines
7.1 KiB
C
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/*
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* (C) Copyright 2009-2010
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* Nokia Siemens Networks, michael.lawnick.ext@nsn.com
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*
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* Portions Copyright (C) 2010 - 2016 Cavium, Inc.
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*
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* This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/atomic.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <asm/octeon/octeon.h>
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#include "i2c-octeon-core.h"
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#define DRV_NAME "i2c-octeon"
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/**
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* octeon_i2c_int_enable - enable the CORE interrupt
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* @i2c: The struct octeon_i2c
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*
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* The interrupt will be asserted when there is non-STAT_IDLE state in
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* the SW_TWSI_EOP_TWSI_STAT register.
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*/
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static void octeon_i2c_int_enable(struct octeon_i2c *i2c)
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{
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octeon_i2c_write_int(i2c, TWSI_INT_CORE_EN);
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}
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/* disable the CORE interrupt */
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static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
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{
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/* clear TS/ST/IFLG events */
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octeon_i2c_write_int(i2c, 0);
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}
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/**
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* octeon_i2c_int_enable78 - enable the CORE interrupt
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* @i2c: The struct octeon_i2c
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*
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* The interrupt will be asserted when there is non-STAT_IDLE state in the
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* SW_TWSI_EOP_TWSI_STAT register.
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*/
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static void octeon_i2c_int_enable78(struct octeon_i2c *i2c)
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{
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atomic_inc_return(&i2c->int_enable_cnt);
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enable_irq(i2c->irq);
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}
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static void __octeon_i2c_irq_disable(atomic_t *cnt, int irq)
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{
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int count;
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/*
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* The interrupt can be disabled in two places, but we only
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* want to make the disable_irq_nosync() call once, so keep
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* track with the atomic variable.
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*/
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count = atomic_dec_if_positive(cnt);
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if (count >= 0)
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disable_irq_nosync(irq);
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}
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/* disable the CORE interrupt */
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static void octeon_i2c_int_disable78(struct octeon_i2c *i2c)
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{
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__octeon_i2c_irq_disable(&i2c->int_enable_cnt, i2c->irq);
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}
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/**
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* octeon_i2c_hlc_int_enable78 - enable the ST interrupt
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* @i2c: The struct octeon_i2c
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*
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* The interrupt will be asserted when there is non-STAT_IDLE state in
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* the SW_TWSI_EOP_TWSI_STAT register.
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*/
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static void octeon_i2c_hlc_int_enable78(struct octeon_i2c *i2c)
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{
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atomic_inc_return(&i2c->hlc_int_enable_cnt);
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enable_irq(i2c->hlc_irq);
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}
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/* disable the ST interrupt */
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static void octeon_i2c_hlc_int_disable78(struct octeon_i2c *i2c)
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{
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__octeon_i2c_irq_disable(&i2c->hlc_int_enable_cnt, i2c->hlc_irq);
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}
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/* HLC interrupt service routine */
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static irqreturn_t octeon_i2c_hlc_isr78(int irq, void *dev_id)
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{
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struct octeon_i2c *i2c = dev_id;
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i2c->hlc_int_disable(i2c);
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wake_up(&i2c->queue);
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return IRQ_HANDLED;
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}
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static void octeon_i2c_hlc_int_enable(struct octeon_i2c *i2c)
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{
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octeon_i2c_write_int(i2c, TWSI_INT_ST_EN);
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}
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static u32 octeon_i2c_functionality(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
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I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_SMBUS_BLOCK_PROC_CALL;
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}
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static const struct i2c_algorithm octeon_i2c_algo = {
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.master_xfer = octeon_i2c_xfer,
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.functionality = octeon_i2c_functionality,
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};
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static struct i2c_adapter octeon_i2c_ops = {
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.owner = THIS_MODULE,
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.name = "OCTEON adapter",
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.algo = &octeon_i2c_algo,
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};
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static int octeon_i2c_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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int irq, result = 0, hlc_irq = 0;
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struct resource *res_mem;
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struct octeon_i2c *i2c;
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bool cn78xx_style;
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cn78xx_style = of_device_is_compatible(node, "cavium,octeon-7890-twsi");
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if (cn78xx_style) {
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hlc_irq = platform_get_irq(pdev, 0);
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if (hlc_irq < 0)
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return hlc_irq;
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irq = platform_get_irq(pdev, 2);
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if (irq < 0)
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return irq;
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} else {
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/* All adaptors have an irq. */
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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}
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i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
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if (!i2c) {
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result = -ENOMEM;
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goto out;
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}
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i2c->dev = &pdev->dev;
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i2c->roff.sw_twsi = 0x00;
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i2c->roff.twsi_int = 0x10;
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i2c->roff.sw_twsi_ext = 0x18;
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res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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i2c->twsi_base = devm_ioremap_resource(&pdev->dev, res_mem);
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if (IS_ERR(i2c->twsi_base)) {
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result = PTR_ERR(i2c->twsi_base);
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goto out;
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}
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/*
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* "clock-rate" is a legacy binding, the official binding is
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* "clock-frequency". Try the official one first and then
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* fall back if it doesn't exist.
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*/
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if (of_property_read_u32(node, "clock-frequency", &i2c->twsi_freq) &&
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of_property_read_u32(node, "clock-rate", &i2c->twsi_freq)) {
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dev_err(i2c->dev,
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"no I2C 'clock-rate' or 'clock-frequency' property\n");
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result = -ENXIO;
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goto out;
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}
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i2c->sys_freq = octeon_get_io_clock_rate();
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init_waitqueue_head(&i2c->queue);
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i2c->irq = irq;
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if (cn78xx_style) {
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i2c->hlc_irq = hlc_irq;
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i2c->int_enable = octeon_i2c_int_enable78;
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i2c->int_disable = octeon_i2c_int_disable78;
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i2c->hlc_int_enable = octeon_i2c_hlc_int_enable78;
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i2c->hlc_int_disable = octeon_i2c_hlc_int_disable78;
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irq_set_status_flags(i2c->irq, IRQ_NOAUTOEN);
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irq_set_status_flags(i2c->hlc_irq, IRQ_NOAUTOEN);
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result = devm_request_irq(&pdev->dev, i2c->hlc_irq,
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octeon_i2c_hlc_isr78, 0,
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DRV_NAME, i2c);
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if (result < 0) {
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dev_err(i2c->dev, "failed to attach interrupt\n");
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goto out;
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}
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} else {
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i2c->int_enable = octeon_i2c_int_enable;
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i2c->int_disable = octeon_i2c_int_disable;
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i2c->hlc_int_enable = octeon_i2c_hlc_int_enable;
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i2c->hlc_int_disable = octeon_i2c_int_disable;
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}
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result = devm_request_irq(&pdev->dev, i2c->irq,
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octeon_i2c_isr, 0, DRV_NAME, i2c);
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if (result < 0) {
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dev_err(i2c->dev, "failed to attach interrupt\n");
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goto out;
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}
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if (OCTEON_IS_MODEL(OCTEON_CN38XX))
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i2c->broken_irq_check = true;
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result = octeon_i2c_init_lowlevel(i2c);
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if (result) {
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dev_err(i2c->dev, "init low level failed\n");
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goto out;
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}
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octeon_i2c_set_clock(i2c);
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i2c->adap = octeon_i2c_ops;
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i2c->adap.timeout = msecs_to_jiffies(2);
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i2c->adap.retries = 5;
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i2c->adap.bus_recovery_info = &octeon_i2c_recovery_info;
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i2c->adap.dev.parent = &pdev->dev;
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i2c->adap.dev.of_node = node;
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i2c_set_adapdata(&i2c->adap, i2c);
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platform_set_drvdata(pdev, i2c);
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result = i2c_add_adapter(&i2c->adap);
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if (result < 0)
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goto out;
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dev_info(i2c->dev, "probed\n");
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return 0;
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out:
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return result;
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};
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static int octeon_i2c_remove(struct platform_device *pdev)
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{
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struct octeon_i2c *i2c = platform_get_drvdata(pdev);
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i2c_del_adapter(&i2c->adap);
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return 0;
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};
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static const struct of_device_id octeon_i2c_match[] = {
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{ .compatible = "cavium,octeon-3860-twsi", },
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{ .compatible = "cavium,octeon-7890-twsi", },
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{},
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};
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MODULE_DEVICE_TABLE(of, octeon_i2c_match);
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static struct platform_driver octeon_i2c_driver = {
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.probe = octeon_i2c_probe,
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.remove = octeon_i2c_remove,
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.driver = {
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.name = DRV_NAME,
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.of_match_table = octeon_i2c_match,
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},
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};
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module_platform_driver(octeon_i2c_driver);
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MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
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MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
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MODULE_LICENSE("GPL");
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