212 lines
6.5 KiB
C
212 lines
6.5 KiB
C
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/*
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* Copyright (c) 1999-2001 Vojtech Pavlik
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* Copyright (c) 2007-2008 Bartlomiej Zolnierkiewicz
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Should you need to contact me, the author, you can do so either by
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* e-mail - mail your message to <vojtech@ucw.cz>, or by paper mail:
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* Vojtech Pavlik, Simunkova 1594, Prague 8, 182 00 Czech Republic
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*/
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#include <linux/kernel.h>
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#include <linux/ide.h>
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#include <linux/module.h>
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/*
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* PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
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* These were taken from ATA/ATAPI-6 standard, rev 0a, except
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* for PIO 5, which is a nonstandard extension and UDMA6, which
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* is currently supported only by Maxtor drives.
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*/
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static struct ide_timing ide_timing[] = {
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{ XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
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{ XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
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{ XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
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{ XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
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{ XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
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{ XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
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{ XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
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{ XFER_MW_DMA_4, 25, 0, 0, 0, 55, 20, 80, 0 },
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{ XFER_MW_DMA_3, 25, 0, 0, 0, 65, 25, 100, 0 },
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{ XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
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{ XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
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{ XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
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{ XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
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{ XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
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{ XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
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{ XFER_PIO_6, 10, 55, 20, 80, 55, 20, 80, 0 },
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{ XFER_PIO_5, 15, 65, 25, 100, 65, 25, 100, 0 },
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{ XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
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{ XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
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{ XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
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{ XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
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{ XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
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{ XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 },
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{ 0xff }
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};
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struct ide_timing *ide_timing_find_mode(u8 speed)
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{
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struct ide_timing *t;
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for (t = ide_timing; t->mode != speed; t++)
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if (t->mode == 0xff)
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return NULL;
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return t;
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}
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EXPORT_SYMBOL_GPL(ide_timing_find_mode);
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u16 ide_pio_cycle_time(ide_drive_t *drive, u8 pio)
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{
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u16 *id = drive->id;
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struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
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u16 cycle = 0;
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if (id[ATA_ID_FIELD_VALID] & 2) {
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if (ata_id_has_iordy(drive->id))
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cycle = id[ATA_ID_EIDE_PIO_IORDY];
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else
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cycle = id[ATA_ID_EIDE_PIO];
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/* conservative "downgrade" for all pre-ATA2 drives */
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if (pio < 3 && cycle < t->cycle)
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cycle = 0; /* use standard timing */
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/* Use the standard timing for the CF specific modes too */
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if (pio > 4 && ata_id_is_cfa(id))
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cycle = 0;
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}
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return cycle ? cycle : t->cycle;
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}
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EXPORT_SYMBOL_GPL(ide_pio_cycle_time);
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#define ENOUGH(v, unit) (((v) - 1) / (unit) + 1)
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#define EZ(v, unit) ((v) ? ENOUGH(v, unit) : 0)
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static void ide_timing_quantize(struct ide_timing *t, struct ide_timing *q,
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int T, int UT)
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{
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q->setup = EZ(t->setup * 1000, T);
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q->act8b = EZ(t->act8b * 1000, T);
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q->rec8b = EZ(t->rec8b * 1000, T);
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q->cyc8b = EZ(t->cyc8b * 1000, T);
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q->active = EZ(t->active * 1000, T);
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q->recover = EZ(t->recover * 1000, T);
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q->cycle = EZ(t->cycle * 1000, T);
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q->udma = EZ(t->udma * 1000, UT);
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}
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void ide_timing_merge(struct ide_timing *a, struct ide_timing *b,
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struct ide_timing *m, unsigned int what)
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{
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if (what & IDE_TIMING_SETUP)
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m->setup = max(a->setup, b->setup);
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if (what & IDE_TIMING_ACT8B)
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m->act8b = max(a->act8b, b->act8b);
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if (what & IDE_TIMING_REC8B)
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m->rec8b = max(a->rec8b, b->rec8b);
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if (what & IDE_TIMING_CYC8B)
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m->cyc8b = max(a->cyc8b, b->cyc8b);
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if (what & IDE_TIMING_ACTIVE)
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m->active = max(a->active, b->active);
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if (what & IDE_TIMING_RECOVER)
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m->recover = max(a->recover, b->recover);
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if (what & IDE_TIMING_CYCLE)
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m->cycle = max(a->cycle, b->cycle);
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if (what & IDE_TIMING_UDMA)
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m->udma = max(a->udma, b->udma);
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}
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EXPORT_SYMBOL_GPL(ide_timing_merge);
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int ide_timing_compute(ide_drive_t *drive, u8 speed,
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struct ide_timing *t, int T, int UT)
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{
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u16 *id = drive->id;
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struct ide_timing *s, p;
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/*
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* Find the mode.
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*/
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s = ide_timing_find_mode(speed);
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if (s == NULL)
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return -EINVAL;
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/*
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* Copy the timing from the table.
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*/
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*t = *s;
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/*
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* If the drive is an EIDE drive, it can tell us it needs extended
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* PIO/MWDMA cycle timing.
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*/
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if (id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
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memset(&p, 0, sizeof(p));
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if (speed >= XFER_PIO_0 && speed < XFER_SW_DMA_0) {
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if (speed <= XFER_PIO_2)
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p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO];
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else if ((speed <= XFER_PIO_4) ||
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(speed == XFER_PIO_5 && !ata_id_is_cfa(id)))
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p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY];
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} else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
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p.cycle = id[ATA_ID_EIDE_DMA_MIN];
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ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B);
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}
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/*
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* Convert the timing to bus clock counts.
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*/
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ide_timing_quantize(t, t, T, UT);
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/*
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* Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
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* S.M.A.R.T and some other commands. We have to ensure that the
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* DMA cycle timing is slower/equal than the current PIO timing.
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*/
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if (speed >= XFER_SW_DMA_0) {
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ide_timing_compute(drive, drive->pio_mode, &p, T, UT);
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ide_timing_merge(&p, t, t, IDE_TIMING_ALL);
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}
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/*
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* Lengthen active & recovery time so that cycle time is correct.
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*/
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if (t->act8b + t->rec8b < t->cyc8b) {
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t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
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t->rec8b = t->cyc8b - t->act8b;
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}
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if (t->active + t->recover < t->cycle) {
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t->active += (t->cycle - (t->active + t->recover)) / 2;
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t->recover = t->cycle - t->active;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(ide_timing_compute);
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