573 lines
17 KiB
C
573 lines
17 KiB
C
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/*
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* Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/spinlock.h>
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#include <linux/pci.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/vmalloc.h>
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#include <linux/moduleparam.h>
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#include "qib.h"
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static unsigned qib_hol_timeout_ms = 3000;
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module_param_named(hol_timeout_ms, qib_hol_timeout_ms, uint, S_IRUGO);
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MODULE_PARM_DESC(hol_timeout_ms,
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"duration of user app suspension after link failure");
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unsigned qib_sdma_fetch_arb = 1;
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module_param_named(fetch_arb, qib_sdma_fetch_arb, uint, S_IRUGO);
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MODULE_PARM_DESC(fetch_arb, "IBA7220: change SDMA descriptor arbitration");
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/**
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* qib_disarm_piobufs - cancel a range of PIO buffers
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* @dd: the qlogic_ib device
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* @first: the first PIO buffer to cancel
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* @cnt: the number of PIO buffers to cancel
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*
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* Cancel a range of PIO buffers. Used at user process close,
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* in case it died while writing to a PIO buffer.
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*/
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void qib_disarm_piobufs(struct qib_devdata *dd, unsigned first, unsigned cnt)
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{
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unsigned long flags;
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unsigned i;
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unsigned last;
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last = first + cnt;
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spin_lock_irqsave(&dd->pioavail_lock, flags);
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for (i = first; i < last; i++) {
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__clear_bit(i, dd->pio_need_disarm);
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dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_BUF(i));
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}
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spin_unlock_irqrestore(&dd->pioavail_lock, flags);
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}
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/*
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* This is called by a user process when it sees the DISARM_BUFS event
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* bit is set.
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*/
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int qib_disarm_piobufs_ifneeded(struct qib_ctxtdata *rcd)
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{
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struct qib_devdata *dd = rcd->dd;
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unsigned i;
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unsigned last;
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unsigned n = 0;
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last = rcd->pio_base + rcd->piocnt;
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/*
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* Don't need uctxt_lock here, since user has called in to us.
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* Clear at start in case more interrupts set bits while we
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* are disarming
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*/
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if (rcd->user_event_mask) {
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/*
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* subctxt_cnt is 0 if not shared, so do base
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* separately, first, then remaining subctxt, if any
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*/
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clear_bit(_QIB_EVENT_DISARM_BUFS_BIT, &rcd->user_event_mask[0]);
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for (i = 1; i < rcd->subctxt_cnt; i++)
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clear_bit(_QIB_EVENT_DISARM_BUFS_BIT,
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&rcd->user_event_mask[i]);
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}
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spin_lock_irq(&dd->pioavail_lock);
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for (i = rcd->pio_base; i < last; i++) {
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if (__test_and_clear_bit(i, dd->pio_need_disarm)) {
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n++;
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dd->f_sendctrl(rcd->ppd, QIB_SENDCTRL_DISARM_BUF(i));
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}
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}
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spin_unlock_irq(&dd->pioavail_lock);
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return 0;
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}
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static struct qib_pportdata *is_sdma_buf(struct qib_devdata *dd, unsigned i)
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{
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struct qib_pportdata *ppd;
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unsigned pidx;
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for (pidx = 0; pidx < dd->num_pports; pidx++) {
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ppd = dd->pport + pidx;
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if (i >= ppd->sdma_state.first_sendbuf &&
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i < ppd->sdma_state.last_sendbuf)
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return ppd;
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}
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return NULL;
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}
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/*
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* Return true if send buffer is being used by a user context.
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* Sets _QIB_EVENT_DISARM_BUFS_BIT in user_event_mask as a side effect
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*/
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static int find_ctxt(struct qib_devdata *dd, unsigned bufn)
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{
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struct qib_ctxtdata *rcd;
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unsigned ctxt;
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int ret = 0;
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spin_lock(&dd->uctxt_lock);
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for (ctxt = dd->first_user_ctxt; ctxt < dd->cfgctxts; ctxt++) {
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rcd = dd->rcd[ctxt];
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if (!rcd || bufn < rcd->pio_base ||
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bufn >= rcd->pio_base + rcd->piocnt)
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continue;
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if (rcd->user_event_mask) {
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int i;
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/*
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* subctxt_cnt is 0 if not shared, so do base
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* separately, first, then remaining subctxt, if any
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*/
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set_bit(_QIB_EVENT_DISARM_BUFS_BIT,
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&rcd->user_event_mask[0]);
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for (i = 1; i < rcd->subctxt_cnt; i++)
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set_bit(_QIB_EVENT_DISARM_BUFS_BIT,
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&rcd->user_event_mask[i]);
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}
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ret = 1;
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break;
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}
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spin_unlock(&dd->uctxt_lock);
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return ret;
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}
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/*
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* Disarm a set of send buffers. If the buffer might be actively being
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* written to, mark the buffer to be disarmed later when it is not being
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* written to.
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*
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* This should only be called from the IRQ error handler.
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*/
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void qib_disarm_piobufs_set(struct qib_devdata *dd, unsigned long *mask,
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unsigned cnt)
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{
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struct qib_pportdata *ppd, *pppd[QIB_MAX_IB_PORTS];
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unsigned i;
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unsigned long flags;
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for (i = 0; i < dd->num_pports; i++)
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pppd[i] = NULL;
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for (i = 0; i < cnt; i++) {
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int which;
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if (!test_bit(i, mask))
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continue;
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/*
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* If the buffer is owned by the DMA hardware,
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* reset the DMA engine.
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*/
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ppd = is_sdma_buf(dd, i);
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if (ppd) {
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pppd[ppd->port] = ppd;
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continue;
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}
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/*
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* If the kernel is writing the buffer or the buffer is
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* owned by a user process, we can't clear it yet.
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*/
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spin_lock_irqsave(&dd->pioavail_lock, flags);
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if (test_bit(i, dd->pio_writing) ||
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(!test_bit(i << 1, dd->pioavailkernel) &&
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find_ctxt(dd, i))) {
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__set_bit(i, dd->pio_need_disarm);
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which = 0;
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} else {
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which = 1;
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dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_BUF(i));
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}
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spin_unlock_irqrestore(&dd->pioavail_lock, flags);
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}
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/* do cancel_sends once per port that had sdma piobufs in error */
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for (i = 0; i < dd->num_pports; i++)
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if (pppd[i])
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qib_cancel_sends(pppd[i]);
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}
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/**
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* update_send_bufs - update shadow copy of the PIO availability map
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* @dd: the qlogic_ib device
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*
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* called whenever our local copy indicates we have run out of send buffers
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*/
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static void update_send_bufs(struct qib_devdata *dd)
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{
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unsigned long flags;
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unsigned i;
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const unsigned piobregs = dd->pioavregs;
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/*
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* If the generation (check) bits have changed, then we update the
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* busy bit for the corresponding PIO buffer. This algorithm will
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* modify positions to the value they already have in some cases
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* (i.e., no change), but it's faster than changing only the bits
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* that have changed.
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*
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* We would like to do this atomicly, to avoid spinlocks in the
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* critical send path, but that's not really possible, given the
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* type of changes, and that this routine could be called on
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* multiple cpu's simultaneously, so we lock in this routine only,
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* to avoid conflicting updates; all we change is the shadow, and
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* it's a single 64 bit memory location, so by definition the update
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* is atomic in terms of what other cpu's can see in testing the
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* bits. The spin_lock overhead isn't too bad, since it only
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* happens when all buffers are in use, so only cpu overhead, not
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* latency or bandwidth is affected.
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*/
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if (!dd->pioavailregs_dma)
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return;
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spin_lock_irqsave(&dd->pioavail_lock, flags);
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for (i = 0; i < piobregs; i++) {
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u64 pchbusy, pchg, piov, pnew;
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piov = le64_to_cpu(dd->pioavailregs_dma[i]);
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pchg = dd->pioavailkernel[i] &
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~(dd->pioavailshadow[i] ^ piov);
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pchbusy = pchg << QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT;
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if (pchg && (pchbusy & dd->pioavailshadow[i])) {
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pnew = dd->pioavailshadow[i] & ~pchbusy;
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pnew |= piov & pchbusy;
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dd->pioavailshadow[i] = pnew;
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}
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}
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spin_unlock_irqrestore(&dd->pioavail_lock, flags);
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}
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/*
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* Debugging code and stats updates if no pio buffers available.
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*/
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static noinline void no_send_bufs(struct qib_devdata *dd)
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{
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dd->upd_pio_shadow = 1;
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/* not atomic, but if we lose a stat count in a while, that's OK */
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qib_stats.sps_nopiobufs++;
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}
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/*
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* Common code for normal driver send buffer allocation, and reserved
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* allocation.
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*
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* Do appropriate marking as busy, etc.
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* Returns buffer pointer if one is found, otherwise NULL.
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*/
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u32 __iomem *qib_getsendbuf_range(struct qib_devdata *dd, u32 *pbufnum,
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u32 first, u32 last)
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{
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unsigned i, j, updated = 0;
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unsigned nbufs;
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unsigned long flags;
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unsigned long *shadow = dd->pioavailshadow;
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u32 __iomem *buf;
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if (!(dd->flags & QIB_PRESENT))
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return NULL;
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nbufs = last - first + 1; /* number in range to check */
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if (dd->upd_pio_shadow) {
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update_shadow:
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/*
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* Minor optimization. If we had no buffers on last call,
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* start out by doing the update; continue and do scan even
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* if no buffers were updated, to be paranoid.
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*/
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update_send_bufs(dd);
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updated++;
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}
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i = first;
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/*
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* While test_and_set_bit() is atomic, we do that and then the
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* change_bit(), and the pair is not. See if this is the cause
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* of the remaining armlaunch errors.
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*/
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spin_lock_irqsave(&dd->pioavail_lock, flags);
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if (dd->last_pio >= first && dd->last_pio <= last)
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i = dd->last_pio + 1;
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if (!first)
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/* adjust to min possible */
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nbufs = last - dd->min_kernel_pio + 1;
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for (j = 0; j < nbufs; j++, i++) {
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if (i > last)
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i = !first ? dd->min_kernel_pio : first;
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if (__test_and_set_bit((2 * i) + 1, shadow))
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continue;
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/* flip generation bit */
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__change_bit(2 * i, shadow);
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/* remember that the buffer can be written to now */
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__set_bit(i, dd->pio_writing);
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if (!first && first != last) /* first == last on VL15, avoid */
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dd->last_pio = i;
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break;
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}
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spin_unlock_irqrestore(&dd->pioavail_lock, flags);
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if (j == nbufs) {
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if (!updated)
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/*
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* First time through; shadow exhausted, but may be
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* buffers available, try an update and then rescan.
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*/
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goto update_shadow;
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no_send_bufs(dd);
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buf = NULL;
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} else {
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if (i < dd->piobcnt2k)
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buf = (u32 __iomem *)(dd->pio2kbase +
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i * dd->palign);
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else if (i < dd->piobcnt2k + dd->piobcnt4k || !dd->piovl15base)
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buf = (u32 __iomem *)(dd->pio4kbase +
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(i - dd->piobcnt2k) * dd->align4k);
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else
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buf = (u32 __iomem *)(dd->piovl15base +
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(i - (dd->piobcnt2k + dd->piobcnt4k)) *
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dd->align4k);
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if (pbufnum)
|
||
|
|
*pbufnum = i;
|
||
|
|
dd->upd_pio_shadow = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
return buf;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Record that the caller is finished writing to the buffer so we don't
|
||
|
|
* disarm it while it is being written and disarm it now if needed.
|
||
|
|
*/
|
||
|
|
void qib_sendbuf_done(struct qib_devdata *dd, unsigned n)
|
||
|
|
{
|
||
|
|
unsigned long flags;
|
||
|
|
|
||
|
|
spin_lock_irqsave(&dd->pioavail_lock, flags);
|
||
|
|
__clear_bit(n, dd->pio_writing);
|
||
|
|
if (__test_and_clear_bit(n, dd->pio_need_disarm))
|
||
|
|
dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_BUF(n));
|
||
|
|
spin_unlock_irqrestore(&dd->pioavail_lock, flags);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* qib_chg_pioavailkernel - change which send buffers are available for kernel
|
||
|
|
* @dd: the qlogic_ib device
|
||
|
|
* @start: the starting send buffer number
|
||
|
|
* @len: the number of send buffers
|
||
|
|
* @avail: true if the buffers are available for kernel use, false otherwise
|
||
|
|
*/
|
||
|
|
void qib_chg_pioavailkernel(struct qib_devdata *dd, unsigned start,
|
||
|
|
unsigned len, u32 avail, struct qib_ctxtdata *rcd)
|
||
|
|
{
|
||
|
|
unsigned long flags;
|
||
|
|
unsigned end;
|
||
|
|
unsigned ostart = start;
|
||
|
|
|
||
|
|
/* There are two bits per send buffer (busy and generation) */
|
||
|
|
start *= 2;
|
||
|
|
end = start + len * 2;
|
||
|
|
|
||
|
|
spin_lock_irqsave(&dd->pioavail_lock, flags);
|
||
|
|
/* Set or clear the busy bit in the shadow. */
|
||
|
|
while (start < end) {
|
||
|
|
if (avail) {
|
||
|
|
unsigned long dma;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* The BUSY bit will never be set, because we disarm
|
||
|
|
* the user buffers before we hand them back to the
|
||
|
|
* kernel. We do have to make sure the generation
|
||
|
|
* bit is set correctly in shadow, since it could
|
||
|
|
* have changed many times while allocated to user.
|
||
|
|
* We can't use the bitmap functions on the full
|
||
|
|
* dma array because it is always little-endian, so
|
||
|
|
* we have to flip to host-order first.
|
||
|
|
* BITS_PER_LONG is slightly wrong, since it's
|
||
|
|
* always 64 bits per register in chip...
|
||
|
|
* We only work on 64 bit kernels, so that's OK.
|
||
|
|
*/
|
||
|
|
i = start / BITS_PER_LONG;
|
||
|
|
__clear_bit(QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT + start,
|
||
|
|
dd->pioavailshadow);
|
||
|
|
dma = (unsigned long)
|
||
|
|
le64_to_cpu(dd->pioavailregs_dma[i]);
|
||
|
|
if (test_bit((QLOGIC_IB_SENDPIOAVAIL_CHECK_SHIFT +
|
||
|
|
start) % BITS_PER_LONG, &dma))
|
||
|
|
__set_bit(QLOGIC_IB_SENDPIOAVAIL_CHECK_SHIFT +
|
||
|
|
start, dd->pioavailshadow);
|
||
|
|
else
|
||
|
|
__clear_bit(QLOGIC_IB_SENDPIOAVAIL_CHECK_SHIFT
|
||
|
|
+ start, dd->pioavailshadow);
|
||
|
|
__set_bit(start, dd->pioavailkernel);
|
||
|
|
if ((start >> 1) < dd->min_kernel_pio)
|
||
|
|
dd->min_kernel_pio = start >> 1;
|
||
|
|
} else {
|
||
|
|
__set_bit(start + QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT,
|
||
|
|
dd->pioavailshadow);
|
||
|
|
__clear_bit(start, dd->pioavailkernel);
|
||
|
|
if ((start >> 1) > dd->min_kernel_pio)
|
||
|
|
dd->min_kernel_pio = start >> 1;
|
||
|
|
}
|
||
|
|
start += 2;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (dd->min_kernel_pio > 0 && dd->last_pio < dd->min_kernel_pio - 1)
|
||
|
|
dd->last_pio = dd->min_kernel_pio - 1;
|
||
|
|
spin_unlock_irqrestore(&dd->pioavail_lock, flags);
|
||
|
|
|
||
|
|
dd->f_txchk_change(dd, ostart, len, avail, rcd);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Flush all sends that might be in the ready to send state, as well as any
|
||
|
|
* that are in the process of being sent. Used whenever we need to be
|
||
|
|
* sure the send side is idle. Cleans up all buffer state by canceling
|
||
|
|
* all pio buffers, and issuing an abort, which cleans up anything in the
|
||
|
|
* launch fifo. The cancel is superfluous on some chip versions, but
|
||
|
|
* it's safer to always do it.
|
||
|
|
* PIOAvail bits are updated by the chip as if a normal send had happened.
|
||
|
|
*/
|
||
|
|
void qib_cancel_sends(struct qib_pportdata *ppd)
|
||
|
|
{
|
||
|
|
struct qib_devdata *dd = ppd->dd;
|
||
|
|
struct qib_ctxtdata *rcd;
|
||
|
|
unsigned long flags;
|
||
|
|
unsigned ctxt;
|
||
|
|
unsigned i;
|
||
|
|
unsigned last;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Tell PSM to disarm buffers again before trying to reuse them.
|
||
|
|
* We need to be sure the rcd doesn't change out from under us
|
||
|
|
* while we do so. We hold the two locks sequentially. We might
|
||
|
|
* needlessly set some need_disarm bits as a result, if the
|
||
|
|
* context is closed after we release the uctxt_lock, but that's
|
||
|
|
* fairly benign, and safer than nesting the locks.
|
||
|
|
*/
|
||
|
|
for (ctxt = dd->first_user_ctxt; ctxt < dd->cfgctxts; ctxt++) {
|
||
|
|
spin_lock_irqsave(&dd->uctxt_lock, flags);
|
||
|
|
rcd = dd->rcd[ctxt];
|
||
|
|
if (rcd && rcd->ppd == ppd) {
|
||
|
|
last = rcd->pio_base + rcd->piocnt;
|
||
|
|
if (rcd->user_event_mask) {
|
||
|
|
/*
|
||
|
|
* subctxt_cnt is 0 if not shared, so do base
|
||
|
|
* separately, first, then remaining subctxt,
|
||
|
|
* if any
|
||
|
|
*/
|
||
|
|
set_bit(_QIB_EVENT_DISARM_BUFS_BIT,
|
||
|
|
&rcd->user_event_mask[0]);
|
||
|
|
for (i = 1; i < rcd->subctxt_cnt; i++)
|
||
|
|
set_bit(_QIB_EVENT_DISARM_BUFS_BIT,
|
||
|
|
&rcd->user_event_mask[i]);
|
||
|
|
}
|
||
|
|
i = rcd->pio_base;
|
||
|
|
spin_unlock_irqrestore(&dd->uctxt_lock, flags);
|
||
|
|
spin_lock_irqsave(&dd->pioavail_lock, flags);
|
||
|
|
for (; i < last; i++)
|
||
|
|
__set_bit(i, dd->pio_need_disarm);
|
||
|
|
spin_unlock_irqrestore(&dd->pioavail_lock, flags);
|
||
|
|
} else
|
||
|
|
spin_unlock_irqrestore(&dd->uctxt_lock, flags);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!(dd->flags & QIB_HAS_SEND_DMA))
|
||
|
|
dd->f_sendctrl(ppd, QIB_SENDCTRL_DISARM_ALL |
|
||
|
|
QIB_SENDCTRL_FLUSH);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Force an update of in-memory copy of the pioavail registers, when
|
||
|
|
* needed for any of a variety of reasons.
|
||
|
|
* If already off, this routine is a nop, on the assumption that the
|
||
|
|
* caller (or set of callers) will "do the right thing".
|
||
|
|
* This is a per-device operation, so just the first port.
|
||
|
|
*/
|
||
|
|
void qib_force_pio_avail_update(struct qib_devdata *dd)
|
||
|
|
{
|
||
|
|
dd->f_sendctrl(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
|
||
|
|
}
|
||
|
|
|
||
|
|
void qib_hol_down(struct qib_pportdata *ppd)
|
||
|
|
{
|
||
|
|
/*
|
||
|
|
* Cancel sends when the link goes DOWN so that we aren't doing it
|
||
|
|
* at INIT when we might be trying to send SMI packets.
|
||
|
|
*/
|
||
|
|
if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
|
||
|
|
qib_cancel_sends(ppd);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Link is at INIT.
|
||
|
|
* We start the HoL timer so we can detect stuck packets blocking SMP replies.
|
||
|
|
* Timer may already be running, so use mod_timer, not add_timer.
|
||
|
|
*/
|
||
|
|
void qib_hol_init(struct qib_pportdata *ppd)
|
||
|
|
{
|
||
|
|
if (ppd->hol_state != QIB_HOL_INIT) {
|
||
|
|
ppd->hol_state = QIB_HOL_INIT;
|
||
|
|
mod_timer(&ppd->hol_timer,
|
||
|
|
jiffies + msecs_to_jiffies(qib_hol_timeout_ms));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Link is up, continue any user processes, and ensure timer
|
||
|
|
* is a nop, if running. Let timer keep running, if set; it
|
||
|
|
* will nop when it sees the link is up.
|
||
|
|
*/
|
||
|
|
void qib_hol_up(struct qib_pportdata *ppd)
|
||
|
|
{
|
||
|
|
ppd->hol_state = QIB_HOL_UP;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This is only called via the timer.
|
||
|
|
*/
|
||
|
|
void qib_hol_event(unsigned long opaque)
|
||
|
|
{
|
||
|
|
struct qib_pportdata *ppd = (struct qib_pportdata *)opaque;
|
||
|
|
|
||
|
|
/* If hardware error, etc, skip. */
|
||
|
|
if (!(ppd->dd->flags & QIB_INITTED))
|
||
|
|
return;
|
||
|
|
|
||
|
|
if (ppd->hol_state != QIB_HOL_UP) {
|
||
|
|
/*
|
||
|
|
* Try to flush sends in case a stuck packet is blocking
|
||
|
|
* SMP replies.
|
||
|
|
*/
|
||
|
|
qib_hol_down(ppd);
|
||
|
|
mod_timer(&ppd->hol_timer,
|
||
|
|
jiffies + msecs_to_jiffies(qib_hol_timeout_ms));
|
||
|
|
}
|
||
|
|
}
|