288 lines
7.8 KiB
C
288 lines
7.8 KiB
C
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/*
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* drivers/media/i2c/tvp514x_regs.h
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*
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* Copyright (C) 2008 Texas Instruments Inc
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* Author: Vaibhav Hiremath <hvaibhav@ti.com>
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*
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* Contributors:
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* Sivaraj R <sivaraj@ti.com>
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* Brijesh R Jadav <brijesh.j@ti.com>
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* Hardik Shah <hardik.shah@ti.com>
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* Manjunath Hadli <mrh@ti.com>
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* Karicheri Muralidharan <m-karicheri2@ti.com>
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*
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* This package is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#ifndef _TVP514X_REGS_H
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#define _TVP514X_REGS_H
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/*
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* TVP5146/47 registers
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*/
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#define REG_INPUT_SEL (0x00)
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#define REG_AFE_GAIN_CTRL (0x01)
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#define REG_VIDEO_STD (0x02)
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#define REG_OPERATION_MODE (0x03)
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#define REG_AUTOSWITCH_MASK (0x04)
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#define REG_COLOR_KILLER (0x05)
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#define REG_LUMA_CONTROL1 (0x06)
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#define REG_LUMA_CONTROL2 (0x07)
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#define REG_LUMA_CONTROL3 (0x08)
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#define REG_BRIGHTNESS (0x09)
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#define REG_CONTRAST (0x0A)
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#define REG_SATURATION (0x0B)
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#define REG_HUE (0x0C)
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#define REG_CHROMA_CONTROL1 (0x0D)
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#define REG_CHROMA_CONTROL2 (0x0E)
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/* 0x0F Reserved */
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#define REG_COMP_PR_SATURATION (0x10)
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#define REG_COMP_Y_CONTRAST (0x11)
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#define REG_COMP_PB_SATURATION (0x12)
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/* 0x13 Reserved */
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#define REG_COMP_Y_BRIGHTNESS (0x14)
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/* 0x15 Reserved */
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#define REG_AVID_START_PIXEL_LSB (0x16)
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#define REG_AVID_START_PIXEL_MSB (0x17)
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#define REG_AVID_STOP_PIXEL_LSB (0x18)
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#define REG_AVID_STOP_PIXEL_MSB (0x19)
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#define REG_HSYNC_START_PIXEL_LSB (0x1A)
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#define REG_HSYNC_START_PIXEL_MSB (0x1B)
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#define REG_HSYNC_STOP_PIXEL_LSB (0x1C)
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#define REG_HSYNC_STOP_PIXEL_MSB (0x1D)
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#define REG_VSYNC_START_LINE_LSB (0x1E)
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#define REG_VSYNC_START_LINE_MSB (0x1F)
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#define REG_VSYNC_STOP_LINE_LSB (0x20)
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#define REG_VSYNC_STOP_LINE_MSB (0x21)
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#define REG_VBLK_START_LINE_LSB (0x22)
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#define REG_VBLK_START_LINE_MSB (0x23)
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#define REG_VBLK_STOP_LINE_LSB (0x24)
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#define REG_VBLK_STOP_LINE_MSB (0x25)
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/* 0x26 - 0x27 Reserved */
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#define REG_FAST_SWTICH_CONTROL (0x28)
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/* 0x29 Reserved */
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#define REG_FAST_SWTICH_SCART_DELAY (0x2A)
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/* 0x2B Reserved */
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#define REG_SCART_DELAY (0x2C)
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#define REG_CTI_DELAY (0x2D)
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#define REG_CTI_CONTROL (0x2E)
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/* 0x2F - 0x31 Reserved */
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#define REG_SYNC_CONTROL (0x32)
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#define REG_OUTPUT_FORMATTER1 (0x33)
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#define REG_OUTPUT_FORMATTER2 (0x34)
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#define REG_OUTPUT_FORMATTER3 (0x35)
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#define REG_OUTPUT_FORMATTER4 (0x36)
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#define REG_OUTPUT_FORMATTER5 (0x37)
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#define REG_OUTPUT_FORMATTER6 (0x38)
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#define REG_CLEAR_LOST_LOCK (0x39)
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#define REG_STATUS1 (0x3A)
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#define REG_STATUS2 (0x3B)
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#define REG_AGC_GAIN_STATUS_LSB (0x3C)
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#define REG_AGC_GAIN_STATUS_MSB (0x3D)
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/* 0x3E Reserved */
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#define REG_VIDEO_STD_STATUS (0x3F)
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#define REG_GPIO_INPUT1 (0x40)
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#define REG_GPIO_INPUT2 (0x41)
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/* 0x42 - 0x45 Reserved */
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#define REG_AFE_COARSE_GAIN_CH1 (0x46)
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#define REG_AFE_COARSE_GAIN_CH2 (0x47)
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#define REG_AFE_COARSE_GAIN_CH3 (0x48)
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#define REG_AFE_COARSE_GAIN_CH4 (0x49)
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#define REG_AFE_FINE_GAIN_PB_B_LSB (0x4A)
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#define REG_AFE_FINE_GAIN_PB_B_MSB (0x4B)
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#define REG_AFE_FINE_GAIN_Y_G_CHROMA_LSB (0x4C)
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#define REG_AFE_FINE_GAIN_Y_G_CHROMA_MSB (0x4D)
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#define REG_AFE_FINE_GAIN_PR_R_LSB (0x4E)
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#define REG_AFE_FINE_GAIN_PR_R_MSB (0x4F)
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#define REG_AFE_FINE_GAIN_CVBS_LUMA_LSB (0x50)
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#define REG_AFE_FINE_GAIN_CVBS_LUMA_MSB (0x51)
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/* 0x52 - 0x68 Reserved */
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#define REG_FBIT_VBIT_CONTROL1 (0x69)
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/* 0x6A - 0x6B Reserved */
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#define REG_BACKEND_AGC_CONTROL (0x6C)
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/* 0x6D - 0x6E Reserved */
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#define REG_AGC_DECREMENT_SPEED_CONTROL (0x6F)
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#define REG_ROM_VERSION (0x70)
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/* 0x71 - 0x73 Reserved */
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#define REG_AGC_WHITE_PEAK_PROCESSING (0x74)
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#define REG_FBIT_VBIT_CONTROL2 (0x75)
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#define REG_VCR_TRICK_MODE_CONTROL (0x76)
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#define REG_HORIZONTAL_SHAKE_INCREMENT (0x77)
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#define REG_AGC_INCREMENT_SPEED (0x78)
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#define REG_AGC_INCREMENT_DELAY (0x79)
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/* 0x7A - 0x7F Reserved */
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#define REG_CHIP_ID_MSB (0x80)
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#define REG_CHIP_ID_LSB (0x81)
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/* 0x82 Reserved */
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#define REG_CPLL_SPEED_CONTROL (0x83)
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/* 0x84 - 0x96 Reserved */
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#define REG_STATUS_REQUEST (0x97)
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/* 0x98 - 0x99 Reserved */
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#define REG_VERTICAL_LINE_COUNT_LSB (0x9A)
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#define REG_VERTICAL_LINE_COUNT_MSB (0x9B)
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/* 0x9C - 0x9D Reserved */
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#define REG_AGC_DECREMENT_DELAY (0x9E)
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/* 0x9F - 0xB0 Reserved */
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#define REG_VDP_TTX_FILTER_1_MASK1 (0xB1)
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#define REG_VDP_TTX_FILTER_1_MASK2 (0xB2)
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#define REG_VDP_TTX_FILTER_1_MASK3 (0xB3)
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#define REG_VDP_TTX_FILTER_1_MASK4 (0xB4)
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#define REG_VDP_TTX_FILTER_1_MASK5 (0xB5)
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#define REG_VDP_TTX_FILTER_2_MASK1 (0xB6)
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#define REG_VDP_TTX_FILTER_2_MASK2 (0xB7)
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#define REG_VDP_TTX_FILTER_2_MASK3 (0xB8)
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#define REG_VDP_TTX_FILTER_2_MASK4 (0xB9)
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#define REG_VDP_TTX_FILTER_2_MASK5 (0xBA)
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#define REG_VDP_TTX_FILTER_CONTROL (0xBB)
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#define REG_VDP_FIFO_WORD_COUNT (0xBC)
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#define REG_VDP_FIFO_INTERRUPT_THRLD (0xBD)
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/* 0xBE Reserved */
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#define REG_VDP_FIFO_RESET (0xBF)
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#define REG_VDP_FIFO_OUTPUT_CONTROL (0xC0)
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#define REG_VDP_LINE_NUMBER_INTERRUPT (0xC1)
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#define REG_VDP_PIXEL_ALIGNMENT_LSB (0xC2)
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#define REG_VDP_PIXEL_ALIGNMENT_MSB (0xC3)
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/* 0xC4 - 0xD5 Reserved */
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#define REG_VDP_LINE_START (0xD6)
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#define REG_VDP_LINE_STOP (0xD7)
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#define REG_VDP_GLOBAL_LINE_MODE (0xD8)
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#define REG_VDP_FULL_FIELD_ENABLE (0xD9)
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#define REG_VDP_FULL_FIELD_MODE (0xDA)
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/* 0xDB - 0xDF Reserved */
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#define REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR (0xE0)
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#define REG_VBUS_DATA_ACCESS_VBUS_ADDR_INCR (0xE1)
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#define REG_FIFO_READ_DATA (0xE2)
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/* 0xE3 - 0xE7 Reserved */
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#define REG_VBUS_ADDRESS_ACCESS1 (0xE8)
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#define REG_VBUS_ADDRESS_ACCESS2 (0xE9)
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#define REG_VBUS_ADDRESS_ACCESS3 (0xEA)
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/* 0xEB - 0xEF Reserved */
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#define REG_INTERRUPT_RAW_STATUS0 (0xF0)
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#define REG_INTERRUPT_RAW_STATUS1 (0xF1)
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#define REG_INTERRUPT_STATUS0 (0xF2)
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#define REG_INTERRUPT_STATUS1 (0xF3)
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#define REG_INTERRUPT_MASK0 (0xF4)
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#define REG_INTERRUPT_MASK1 (0xF5)
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#define REG_INTERRUPT_CLEAR0 (0xF6)
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#define REG_INTERRUPT_CLEAR1 (0xF7)
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/* 0xF8 - 0xFF Reserved */
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/*
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* Mask and bit definitions of TVP5146/47 registers
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*/
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/* The ID values we are looking for */
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#define TVP514X_CHIP_ID_MSB (0x51)
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#define TVP5146_CHIP_ID_LSB (0x46)
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#define TVP5147_CHIP_ID_LSB (0x47)
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#define VIDEO_STD_MASK (0x07)
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#define VIDEO_STD_AUTO_SWITCH_BIT (0x00)
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#define VIDEO_STD_NTSC_MJ_BIT (0x01)
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#define VIDEO_STD_PAL_BDGHIN_BIT (0x02)
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#define VIDEO_STD_PAL_M_BIT (0x03)
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#define VIDEO_STD_PAL_COMBINATION_N_BIT (0x04)
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#define VIDEO_STD_NTSC_4_43_BIT (0x05)
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#define VIDEO_STD_SECAM_BIT (0x06)
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#define VIDEO_STD_PAL_60_BIT (0x07)
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/*
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* Status bit
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*/
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#define STATUS_TV_VCR_BIT (1<<0)
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#define STATUS_HORZ_SYNC_LOCK_BIT (1<<1)
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#define STATUS_VIRT_SYNC_LOCK_BIT (1<<2)
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#define STATUS_CLR_SUBCAR_LOCK_BIT (1<<3)
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#define STATUS_LOST_LOCK_DETECT_BIT (1<<4)
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#define STATUS_FEILD_RATE_BIT (1<<5)
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#define STATUS_LINE_ALTERNATING_BIT (1<<6)
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#define STATUS_PEAK_WHITE_DETECT_BIT (1<<7)
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/* Tokens for register write */
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#define TOK_WRITE (0) /* token for write operation */
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#define TOK_TERM (1) /* terminating token */
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#define TOK_DELAY (2) /* delay token for reg list */
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#define TOK_SKIP (3) /* token to skip a register */
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/**
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* struct tvp514x_reg - Structure for TVP5146/47 register initialization values
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* @token - Token: TOK_WRITE, TOK_TERM etc..
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* @reg - Register offset
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* @val - Register Value for TOK_WRITE or delay in ms for TOK_DELAY
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*/
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struct tvp514x_reg {
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u8 token;
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u8 reg;
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u32 val;
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};
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#endif /* ifndef _TVP514X_REGS_H */
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