141 lines
4.7 KiB
C
141 lines
4.7 KiB
C
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/*
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* TI AM437x Image Sensor Interface Registers
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*
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* Copyright (C) 2013 - 2014 Texas Instruments, Inc.
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*
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* Benoit Parrot <bparrot@ti.com>
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* Lad, Prabhakar <prabhakar.csengg@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef AM437X_VPFE_REGS_H
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#define AM437X_VPFE_REGS_H
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/* VPFE module register offset */
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#define VPFE_REVISION 0x0
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#define VPFE_PCR 0x4
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#define VPFE_SYNMODE 0x8
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#define VPFE_HD_VD_WID 0xc
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#define VPFE_PIX_LINES 0x10
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#define VPFE_HORZ_INFO 0x14
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#define VPFE_VERT_START 0x18
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#define VPFE_VERT_LINES 0x1c
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#define VPFE_CULLING 0x20
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#define VPFE_HSIZE_OFF 0x24
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#define VPFE_SDOFST 0x28
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#define VPFE_SDR_ADDR 0x2c
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#define VPFE_CLAMP 0x30
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#define VPFE_DCSUB 0x34
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#define VPFE_COLPTN 0x38
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#define VPFE_BLKCMP 0x3c
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#define VPFE_VDINT 0x48
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#define VPFE_ALAW 0x4c
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#define VPFE_REC656IF 0x50
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#define VPFE_CCDCFG 0x54
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#define VPFE_DMA_CNTL 0x98
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#define VPFE_SYSCONFIG 0x104
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#define VPFE_CONFIG 0x108
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#define VPFE_IRQ_EOI 0x110
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#define VPFE_IRQ_STS_RAW 0x114
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#define VPFE_IRQ_STS 0x118
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#define VPFE_IRQ_EN_SET 0x11c
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#define VPFE_IRQ_EN_CLR 0x120
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#define VPFE_REG_END 0x124
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/* Define bit fields within selected registers */
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#define VPFE_FID_POL_MASK 1
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#define VPFE_FID_POL_SHIFT 4
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#define VPFE_HD_POL_MASK 1
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#define VPFE_HD_POL_SHIFT 3
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#define VPFE_VD_POL_MASK 1
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#define VPFE_VD_POL_SHIFT 2
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#define VPFE_HSIZE_OFF_MASK 0xffffffe0
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#define VPFE_32BYTE_ALIGN_VAL 31
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#define VPFE_FRM_FMT_MASK 0x1
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#define VPFE_FRM_FMT_SHIFT 7
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#define VPFE_DATA_SZ_MASK 7
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#define VPFE_DATA_SZ_SHIFT 8
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#define VPFE_PIX_FMT_MASK 3
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#define VPFE_PIX_FMT_SHIFT 12
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#define VPFE_VP2SDR_DISABLE 0xfffbffff
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#define VPFE_WEN_ENABLE (1 << 17)
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#define VPFE_SDR2RSZ_DISABLE 0xfff7ffff
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#define VPFE_VDHDEN_ENABLE (1 << 16)
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#define VPFE_LPF_ENABLE (1 << 14)
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#define VPFE_ALAW_ENABLE (1 << 3)
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#define VPFE_ALAW_GAMMA_WD_MASK 7
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#define VPFE_BLK_CLAMP_ENABLE (1 << 31)
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#define VPFE_BLK_SGAIN_MASK 0x1f
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#define VPFE_BLK_ST_PXL_MASK 0x7fff
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#define VPFE_BLK_ST_PXL_SHIFT 10
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#define VPFE_BLK_SAMPLE_LN_MASK 7
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#define VPFE_BLK_SAMPLE_LN_SHIFT 28
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#define VPFE_BLK_SAMPLE_LINE_MASK 7
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#define VPFE_BLK_SAMPLE_LINE_SHIFT 25
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#define VPFE_BLK_DC_SUB_MASK 0x03fff
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#define VPFE_BLK_COMP_MASK 0xff
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#define VPFE_BLK_COMP_GB_COMP_SHIFT 8
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#define VPFE_BLK_COMP_GR_COMP_SHIFT 16
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#define VPFE_BLK_COMP_R_COMP_SHIFT 24
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#define VPFE_LATCH_ON_VSYNC_DISABLE (1 << 15)
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#define VPFE_DATA_PACK_ENABLE (1 << 11)
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#define VPFE_HORZ_INFO_SPH_SHIFT 16
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#define VPFE_VERT_START_SLV0_SHIFT 16
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#define VPFE_VDINT_VDINT0_SHIFT 16
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#define VPFE_VDINT_VDINT1_MASK 0xffff
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#define VPFE_PPC_RAW 1
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#define VPFE_DCSUB_DEFAULT_VAL 0
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#define VPFE_CLAMP_DEFAULT_VAL 0
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#define VPFE_COLPTN_VAL 0xbb11bb11
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#define VPFE_TWO_BYTES_PER_PIXEL 2
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#define VPFE_INTERLACED_IMAGE_INVERT 0x4b6d
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#define VPFE_INTERLACED_NO_IMAGE_INVERT 0x0249
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#define VPFE_PROGRESSIVE_IMAGE_INVERT 0x4000
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#define VPFE_PROGRESSIVE_NO_IMAGE_INVERT 0
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#define VPFE_INTERLACED_HEIGHT_SHIFT 1
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#define VPFE_SYN_MODE_INPMOD_SHIFT 12
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#define VPFE_SYN_MODE_INPMOD_MASK 3
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#define VPFE_SYN_MODE_8BITS (7 << 8)
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#define VPFE_SYN_MODE_10BITS (6 << 8)
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#define VPFE_SYN_MODE_11BITS (5 << 8)
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#define VPFE_SYN_MODE_12BITS (4 << 8)
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#define VPFE_SYN_MODE_13BITS (3 << 8)
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#define VPFE_SYN_MODE_14BITS (2 << 8)
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#define VPFE_SYN_MODE_15BITS (1 << 8)
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#define VPFE_SYN_MODE_16BITS (0 << 8)
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#define VPFE_SYN_FLDMODE_MASK 1
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#define VPFE_SYN_FLDMODE_SHIFT 7
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#define VPFE_REC656IF_BT656_EN 3
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#define VPFE_SYN_MODE_VD_POL_NEGATIVE (1 << 2)
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#define VPFE_CCDCFG_Y8POS_SHIFT 11
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#define VPFE_CCDCFG_BW656_10BIT (1 << 5)
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#define VPFE_SDOFST_FIELD_INTERLEAVED 0x249
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#define VPFE_NO_CULLING 0xffff00ff
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#define VPFE_VDINT0 (1 << 0)
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#define VPFE_VDINT1 (1 << 1)
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#define VPFE_VDINT2 (1 << 2)
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#define VPFE_DMA_CNTL_OVERFLOW (1 << 31)
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#define VPFE_CONFIG_PCLK_INV_SHIFT 0
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#define VPFE_CONFIG_PCLK_INV_MASK 1
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#define VPFE_CONFIG_PCLK_INV_NOT_INV 0
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#define VPFE_CONFIG_PCLK_INV_INV 1
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#define VPFE_CONFIG_EN_SHIFT 1
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#define VPFE_CONFIG_EN_MASK 2
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#define VPFE_CONFIG_EN_DISABLE 0
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#define VPFE_CONFIG_EN_ENABLE 1
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#define VPFE_CONFIG_ST_SHIFT 2
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#define VPFE_CONFIG_ST_MASK 4
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#define VPFE_CONFIG_ST_OCP_ACTIVE 0
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#define VPFE_CONFIG_ST_OCP_STANDBY 1
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#endif /* AM437X_VPFE_REGS_H */
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