460 lines
18 KiB
C
460 lines
18 KiB
C
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/*
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* Register definition file for Samsung MFC V5.1 Interface (FIMV) driver
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*
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* Kamil Debski, Copyright (c) 2010 Samsung Electronics
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* http://www.samsung.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _REGS_FIMV_H
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#define _REGS_FIMV_H
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#include <linux/kernel.h>
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#include <linux/sizes.h>
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#define S5P_FIMV_REG_SIZE (S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR)
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#define S5P_FIMV_REG_COUNT ((S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) / 4)
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/* Number of bits that the buffer address should be shifted for particular
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* MFC buffers. */
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#define S5P_FIMV_START_ADDR 0x0000
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#define S5P_FIMV_END_ADDR 0xe008
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#define S5P_FIMV_SW_RESET 0x0000
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#define S5P_FIMV_RISC_HOST_INT 0x0008
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/* Command from HOST to RISC */
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#define S5P_FIMV_HOST2RISC_CMD 0x0030
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#define S5P_FIMV_HOST2RISC_ARG1 0x0034
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#define S5P_FIMV_HOST2RISC_ARG2 0x0038
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#define S5P_FIMV_HOST2RISC_ARG3 0x003c
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#define S5P_FIMV_HOST2RISC_ARG4 0x0040
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/* Command from RISC to HOST */
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#define S5P_FIMV_RISC2HOST_CMD 0x0044
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#define S5P_FIMV_RISC2HOST_CMD_MASK 0x1FFFF
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#define S5P_FIMV_RISC2HOST_ARG1 0x0048
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#define S5P_FIMV_RISC2HOST_ARG2 0x004c
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#define S5P_FIMV_RISC2HOST_ARG3 0x0050
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#define S5P_FIMV_RISC2HOST_ARG4 0x0054
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#define S5P_FIMV_FW_VERSION 0x0058
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#define S5P_FIMV_SYS_MEM_SZ 0x005c
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#define S5P_FIMV_FW_STATUS 0x0080
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/* Memory controller register */
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#define S5P_FIMV_MC_DRAMBASE_ADR_A 0x0508
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#define S5P_FIMV_MC_DRAMBASE_ADR_B 0x050c
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#define S5P_FIMV_MC_STATUS 0x0510
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/* Common register */
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#define S5P_FIMV_COMMON_BASE_A 0x0600
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#define S5P_FIMV_COMMON_BASE_B 0x0700
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/* Decoder */
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#define S5P_FIMV_DEC_CHROMA_ADR (S5P_FIMV_COMMON_BASE_A)
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#define S5P_FIMV_DEC_LUMA_ADR (S5P_FIMV_COMMON_BASE_B)
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/* H.264 decoding */
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#define S5P_FIMV_H264_VERT_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)
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/* vertical neighbor motion vector */
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#define S5P_FIMV_H264_NB_IP_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)
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/* neighbor pixels for intra pred */
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#define S5P_FIMV_H264_MV_ADR (S5P_FIMV_COMMON_BASE_B + 0x80)
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/* H264 motion vector */
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/* MPEG4 decoding */
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#define S5P_FIMV_MPEG4_NB_DCAC_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)
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/* neighbor AC/DC coeff. */
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#define S5P_FIMV_MPEG4_UP_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)
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/* upper neighbor motion vector */
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#define S5P_FIMV_MPEG4_SA_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x94)
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/* subseq. anchor motion vector */
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#define S5P_FIMV_MPEG4_OT_LINE_ADR (S5P_FIMV_COMMON_BASE_A + 0x98)
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/* overlap transform line */
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#define S5P_FIMV_MPEG4_SP_ADR (S5P_FIMV_COMMON_BASE_A + 0xa8)
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/* syntax parser */
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/* H.263 decoding */
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#define S5P_FIMV_H263_NB_DCAC_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)
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#define S5P_FIMV_H263_UP_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)
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#define S5P_FIMV_H263_SA_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x94)
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#define S5P_FIMV_H263_OT_LINE_ADR (S5P_FIMV_COMMON_BASE_A + 0x98)
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/* VC-1 decoding */
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#define S5P_FIMV_VC1_NB_DCAC_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)
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#define S5P_FIMV_VC1_UP_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)
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#define S5P_FIMV_VC1_SA_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x94)
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#define S5P_FIMV_VC1_OT_LINE_ADR (S5P_FIMV_COMMON_BASE_A + 0x98)
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#define S5P_FIMV_VC1_BITPLANE3_ADR (S5P_FIMV_COMMON_BASE_A + 0x9c)
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/* bitplane3 */
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#define S5P_FIMV_VC1_BITPLANE2_ADR (S5P_FIMV_COMMON_BASE_A + 0xa0)
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/* bitplane2 */
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#define S5P_FIMV_VC1_BITPLANE1_ADR (S5P_FIMV_COMMON_BASE_A + 0xa4)
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/* bitplane1 */
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/* Encoder */
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#define S5P_FIMV_ENC_REF0_LUMA_ADR (S5P_FIMV_COMMON_BASE_A + 0x1c)
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#define S5P_FIMV_ENC_REF1_LUMA_ADR (S5P_FIMV_COMMON_BASE_A + 0x20)
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/* reconstructed luma */
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#define S5P_FIMV_ENC_REF0_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B)
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#define S5P_FIMV_ENC_REF1_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x04)
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/* reconstructed chroma */
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#define S5P_FIMV_ENC_REF2_LUMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x10)
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#define S5P_FIMV_ENC_REF2_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x08)
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#define S5P_FIMV_ENC_REF3_LUMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x14)
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#define S5P_FIMV_ENC_REF3_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x0c)
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/* H.264 encoding */
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#define S5P_FIMV_H264_UP_MV_ADR (S5P_FIMV_COMMON_BASE_A)
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/* upper motion vector */
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#define S5P_FIMV_H264_NBOR_INFO_ADR (S5P_FIMV_COMMON_BASE_A + 0x04)
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/* entropy engine's neighbor info. */
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#define S5P_FIMV_H264_UP_INTRA_MD_ADR (S5P_FIMV_COMMON_BASE_A + 0x08)
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/* upper intra MD */
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#define S5P_FIMV_H264_COZERO_FLAG_ADR (S5P_FIMV_COMMON_BASE_A + 0x10)
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/* direct cozero flag */
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#define S5P_FIMV_H264_UP_INTRA_PRED_ADR (S5P_FIMV_COMMON_BASE_B + 0x40)
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/* upper intra PRED */
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/* H.263 encoding */
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#define S5P_FIMV_H263_UP_MV_ADR (S5P_FIMV_COMMON_BASE_A)
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/* upper motion vector */
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#define S5P_FIMV_H263_ACDC_COEF_ADR (S5P_FIMV_COMMON_BASE_A + 0x04)
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/* upper Q coeff. */
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/* MPEG4 encoding */
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#define S5P_FIMV_MPEG4_UP_MV_ADR (S5P_FIMV_COMMON_BASE_A)
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/* upper motion vector */
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#define S5P_FIMV_MPEG4_ACDC_COEF_ADR (S5P_FIMV_COMMON_BASE_A + 0x04)
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/* upper Q coeff. */
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#define S5P_FIMV_MPEG4_COZERO_FLAG_ADR (S5P_FIMV_COMMON_BASE_A + 0x10)
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/* direct cozero flag */
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#define S5P_FIMV_ENC_REF_B_LUMA_ADR 0x062c /* ref B Luma addr */
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#define S5P_FIMV_ENC_REF_B_CHROMA_ADR 0x0630 /* ref B Chroma addr */
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#define S5P_FIMV_ENC_CUR_LUMA_ADR 0x0718 /* current Luma addr */
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#define S5P_FIMV_ENC_CUR_CHROMA_ADR 0x071C /* current Chroma addr */
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/* Codec common register */
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#define S5P_FIMV_ENC_HSIZE_PX 0x0818 /* frame width at encoder */
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#define S5P_FIMV_ENC_VSIZE_PX 0x081c /* frame height at encoder */
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#define S5P_FIMV_ENC_PROFILE 0x0830 /* profile register */
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#define S5P_FIMV_ENC_PROFILE_H264_MAIN 0
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#define S5P_FIMV_ENC_PROFILE_H264_HIGH 1
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#define S5P_FIMV_ENC_PROFILE_H264_BASELINE 2
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#define S5P_FIMV_ENC_PROFILE_H264_CONSTRAINED_BASELINE 3
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#define S5P_FIMV_ENC_PROFILE_MPEG4_SIMPLE 0
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#define S5P_FIMV_ENC_PROFILE_MPEG4_ADVANCED_SIMPLE 1
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#define S5P_FIMV_ENC_PIC_STRUCT 0x083c /* picture field/frame flag */
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#define S5P_FIMV_ENC_LF_CTRL 0x0848 /* loop filter control */
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#define S5P_FIMV_ENC_ALPHA_OFF 0x084c /* loop filter alpha offset */
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#define S5P_FIMV_ENC_BETA_OFF 0x0850 /* loop filter beta offset */
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#define S5P_FIMV_MR_BUSIF_CTRL 0x0854 /* hidden, bus interface ctrl */
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#define S5P_FIMV_ENC_PXL_CACHE_CTRL 0x0a00 /* pixel cache control */
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/* Channel & stream interface register */
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#define S5P_FIMV_SI_RTN_CHID 0x2000 /* Return CH inst ID register */
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#define S5P_FIMV_SI_CH0_INST_ID 0x2040 /* codec instance ID */
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#define S5P_FIMV_SI_CH1_INST_ID 0x2080 /* codec instance ID */
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/* Decoder */
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#define S5P_FIMV_SI_VRESOL 0x2004 /* vertical res of decoder */
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#define S5P_FIMV_SI_HRESOL 0x2008 /* horizontal res of decoder */
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#define S5P_FIMV_SI_BUF_NUMBER 0x200c /* number of frames in the
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decoded pic */
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#define S5P_FIMV_SI_DISPLAY_Y_ADR 0x2010 /* luma addr of displayed pic */
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#define S5P_FIMV_SI_DISPLAY_C_ADR 0x2014 /* chroma addrof displayed pic */
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#define S5P_FIMV_SI_CONSUMED_BYTES 0x2018 /* Consumed number of bytes to
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decode a frame */
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#define S5P_FIMV_SI_DISPLAY_STATUS 0x201c /* status of decoded picture */
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#define S5P_FIMV_SI_DECODE_Y_ADR 0x2024 /* luma addr of decoded pic */
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#define S5P_FIMV_SI_DECODE_C_ADR 0x2028 /* chroma addrof decoded pic */
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#define S5P_FIMV_SI_DECODE_STATUS 0x202c /* status of decoded picture */
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#define S5P_FIMV_SI_CH0_SB_ST_ADR 0x2044 /* start addr of stream buf */
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#define S5P_FIMV_SI_CH0_SB_FRM_SIZE 0x2048 /* size of stream buf */
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#define S5P_FIMV_SI_CH0_DESC_ADR 0x204c /* addr of descriptor buf */
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#define S5P_FIMV_SI_CH0_CPB_SIZE 0x2058 /* max size of coded pic. buf */
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#define S5P_FIMV_SI_CH0_DESC_SIZE 0x205c /* max size of descriptor buf */
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#define S5P_FIMV_SI_CH1_SB_ST_ADR 0x2084 /* start addr of stream buf */
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#define S5P_FIMV_SI_CH1_SB_FRM_SIZE 0x2088 /* size of stream buf */
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#define S5P_FIMV_SI_CH1_DESC_ADR 0x208c /* addr of descriptor buf */
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#define S5P_FIMV_SI_CH1_CPB_SIZE 0x2098 /* max size of coded pic. buf */
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#define S5P_FIMV_SI_CH1_DESC_SIZE 0x209c /* max size of descriptor buf */
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#define S5P_FIMV_CRC_LUMA0 0x2030 /* luma crc data per frame
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(top field) */
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#define S5P_FIMV_CRC_CHROMA0 0x2034 /* chroma crc data per frame
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(top field) */
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#define S5P_FIMV_CRC_LUMA1 0x2038 /* luma crc data per bottom
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field */
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#define S5P_FIMV_CRC_CHROMA1 0x203c /* chroma crc data per bottom
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field */
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/* Display status */
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#define S5P_FIMV_DEC_STATUS_DECODING_ONLY 0
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#define S5P_FIMV_DEC_STATUS_DECODING_DISPLAY 1
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#define S5P_FIMV_DEC_STATUS_DISPLAY_ONLY 2
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#define S5P_FIMV_DEC_STATUS_DECODING_EMPTY 3
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#define S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK 7
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#define S5P_FIMV_DEC_STATUS_PROGRESSIVE (0<<3)
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#define S5P_FIMV_DEC_STATUS_INTERLACE (1<<3)
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#define S5P_FIMV_DEC_STATUS_INTERLACE_MASK (1<<3)
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#define S5P_FIMV_DEC_STATUS_CRC_NUMBER_TWO (0<<4)
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#define S5P_FIMV_DEC_STATUS_CRC_NUMBER_FOUR (1<<4)
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#define S5P_FIMV_DEC_STATUS_CRC_NUMBER_MASK (1<<4)
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#define S5P_FIMV_DEC_STATUS_CRC_GENERATED (1<<5)
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#define S5P_FIMV_DEC_STATUS_CRC_NOT_GENERATED (0<<5)
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#define S5P_FIMV_DEC_STATUS_CRC_MASK (1<<5)
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#define S5P_FIMV_DEC_STATUS_RESOLUTION_MASK (3<<4)
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#define S5P_FIMV_DEC_STATUS_RESOLUTION_INC (1<<4)
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#define S5P_FIMV_DEC_STATUS_RESOLUTION_DEC (2<<4)
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#define S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT 4
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/* Decode frame address */
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#define S5P_FIMV_DECODE_Y_ADR 0x2024
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#define S5P_FIMV_DECODE_C_ADR 0x2028
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/* Decoded frame tpe */
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#define S5P_FIMV_DECODE_FRAME_TYPE 0x2020
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#define S5P_FIMV_DECODE_FRAME_MASK 7
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#define S5P_FIMV_DECODE_FRAME_SKIPPED 0
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#define S5P_FIMV_DECODE_FRAME_I_FRAME 1
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#define S5P_FIMV_DECODE_FRAME_P_FRAME 2
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#define S5P_FIMV_DECODE_FRAME_B_FRAME 3
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#define S5P_FIMV_DECODE_FRAME_OTHER_FRAME 4
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/* Sizes of buffers required for decoding */
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#define S5P_FIMV_DEC_NB_IP_SIZE (32 * 1024)
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#define S5P_FIMV_DEC_VERT_NB_MV_SIZE (16 * 1024)
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#define S5P_FIMV_DEC_NB_DCAC_SIZE (16 * 1024)
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#define S5P_FIMV_DEC_UPNB_MV_SIZE (68 * 1024)
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#define S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE (136 * 1024)
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#define S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE (32 * 1024)
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#define S5P_FIMV_DEC_VC1_BITPLANE_SIZE (2 * 1024)
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#define S5P_FIMV_DEC_STX_PARSER_SIZE (68 * 1024)
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#define S5P_FIMV_DEC_BUF_ALIGN (8 * 1024)
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#define S5P_FIMV_ENC_BUF_ALIGN (8 * 1024)
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#define S5P_FIMV_NV12M_HALIGN 16
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#define S5P_FIMV_NV12M_LVALIGN 16
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#define S5P_FIMV_NV12M_CVALIGN 8
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#define S5P_FIMV_NV12MT_HALIGN 128
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#define S5P_FIMV_NV12MT_VALIGN 32
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#define S5P_FIMV_NV12M_SALIGN 2048
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#define S5P_FIMV_NV12MT_SALIGN 8192
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/* Sizes of buffers required for encoding */
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#define S5P_FIMV_ENC_UPMV_SIZE 0x10000
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#define S5P_FIMV_ENC_COLFLG_SIZE 0x10000
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#define S5P_FIMV_ENC_INTRAMD_SIZE 0x10000
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#define S5P_FIMV_ENC_INTRAPRED_SIZE 0x4000
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#define S5P_FIMV_ENC_NBORINFO_SIZE 0x10000
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#define S5P_FIMV_ENC_ACDCCOEF_SIZE 0x10000
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/* Encoder */
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#define S5P_FIMV_ENC_SI_STRM_SIZE 0x2004 /* stream size */
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#define S5P_FIMV_ENC_SI_PIC_CNT 0x2008 /* picture count */
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#define S5P_FIMV_ENC_SI_WRITE_PTR 0x200c /* write pointer */
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#define S5P_FIMV_ENC_SI_SLICE_TYPE 0x2010 /* slice type(I/P/B/IDR) */
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#define S5P_FIMV_ENC_SI_SLICE_TYPE_NON_CODED 0
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#define S5P_FIMV_ENC_SI_SLICE_TYPE_I 1
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#define S5P_FIMV_ENC_SI_SLICE_TYPE_P 2
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#define S5P_FIMV_ENC_SI_SLICE_TYPE_B 3
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#define S5P_FIMV_ENC_SI_SLICE_TYPE_SKIPPED 4
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#define S5P_FIMV_ENC_SI_SLICE_TYPE_OTHERS 5
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#define S5P_FIMV_ENCODED_Y_ADDR 0x2014 /* the addr of the encoded
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luma pic */
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#define S5P_FIMV_ENCODED_C_ADDR 0x2018 /* the addr of the encoded
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chroma pic */
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#define S5P_FIMV_ENC_SI_CH0_SB_ADR 0x2044 /* addr of stream buf */
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#define S5P_FIMV_ENC_SI_CH0_SB_SIZE 0x204c /* size of stream buf */
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#define S5P_FIMV_ENC_SI_CH0_CUR_Y_ADR 0x2050 /* current Luma addr */
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#define S5P_FIMV_ENC_SI_CH0_CUR_C_ADR 0x2054 /* current Chroma addr */
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#define S5P_FIMV_ENC_SI_CH0_FRAME_INS 0x2058 /* frame insertion */
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#define S5P_FIMV_ENC_SI_CH1_SB_ADR 0x2084 /* addr of stream buf */
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#define S5P_FIMV_ENC_SI_CH1_SB_SIZE 0x208c /* size of stream buf */
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#define S5P_FIMV_ENC_SI_CH1_CUR_Y_ADR 0x2090 /* current Luma addr */
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#define S5P_FIMV_ENC_SI_CH1_CUR_C_ADR 0x2094 /* current Chroma addr */
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#define S5P_FIMV_ENC_SI_CH1_FRAME_INS 0x2098 /* frame insertion */
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#define S5P_FIMV_ENC_PIC_TYPE_CTRL 0xc504 /* pic type level control */
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#define S5P_FIMV_ENC_B_RECON_WRITE_ON 0xc508 /* B frame recon write ctrl */
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#define S5P_FIMV_ENC_MSLICE_CTRL 0xc50c /* multi slice control */
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#define S5P_FIMV_ENC_MSLICE_MB 0xc510 /* MB number in the one slice */
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#define S5P_FIMV_ENC_MSLICE_BIT 0xc514 /* bit count for one slice */
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#define S5P_FIMV_ENC_CIR_CTRL 0xc518 /* number of intra refresh MB */
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#define S5P_FIMV_ENC_MAP_FOR_CUR 0xc51c /* linear or tiled mode */
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#define S5P_FIMV_ENC_PADDING_CTRL 0xc520 /* padding control */
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#define S5P_FIMV_ENC_RC_CONFIG 0xc5a0 /* RC config */
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#define S5P_FIMV_ENC_RC_BIT_RATE 0xc5a8 /* bit rate */
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#define S5P_FIMV_ENC_RC_QBOUND 0xc5ac /* max/min QP */
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#define S5P_FIMV_ENC_RC_RPARA 0xc5b0 /* rate control reaction coeff */
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#define S5P_FIMV_ENC_RC_MB_CTRL 0xc5b4 /* MB adaptive scaling */
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/* Encoder for H264 only */
|
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#define S5P_FIMV_ENC_H264_ENTROPY_MODE 0xd004 /* CAVLC or CABAC */
|
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#define S5P_FIMV_ENC_H264_ALPHA_OFF 0xd008 /* loop filter alpha offset */
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#define S5P_FIMV_ENC_H264_BETA_OFF 0xd00c /* loop filter beta offset */
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#define S5P_FIMV_ENC_H264_NUM_OF_REF 0xd010 /* number of reference for P/B */
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#define S5P_FIMV_ENC_H264_TRANS_FLAG 0xd034 /* 8x8 transform flag in PPS &
|
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high profile */
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#define S5P_FIMV_ENC_RC_FRAME_RATE 0xd0d0 /* frame rate */
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/* Encoder for MPEG4 only */
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#define S5P_FIMV_ENC_MPEG4_QUART_PXL 0xe008 /* qpel interpolation ctrl */
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/* Additional */
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#define S5P_FIMV_SI_CH0_DPB_CONF_CTRL 0x2068 /* DPB Config Control Register */
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#define S5P_FIMV_SLICE_INT_MASK 1
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#define S5P_FIMV_SLICE_INT_SHIFT 31
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#define S5P_FIMV_DDELAY_ENA_SHIFT 30
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#define S5P_FIMV_DDELAY_VAL_MASK 0xff
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#define S5P_FIMV_DDELAY_VAL_SHIFT 16
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#define S5P_FIMV_DPB_COUNT_MASK 0xffff
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#define S5P_FIMV_DPB_FLUSH_MASK 1
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#define S5P_FIMV_DPB_FLUSH_SHIFT 14
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#define S5P_FIMV_SI_CH0_RELEASE_BUF 0x2060 /* DPB release buffer register */
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#define S5P_FIMV_SI_CH0_HOST_WR_ADR 0x2064 /* address of shared memory */
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/* Codec numbers */
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#define S5P_FIMV_CODEC_NONE -1
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#define S5P_FIMV_CODEC_H264_DEC 0
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#define S5P_FIMV_CODEC_VC1_DEC 1
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#define S5P_FIMV_CODEC_MPEG4_DEC 2
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#define S5P_FIMV_CODEC_MPEG2_DEC 3
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#define S5P_FIMV_CODEC_H263_DEC 4
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#define S5P_FIMV_CODEC_VC1RCV_DEC 5
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#define S5P_FIMV_CODEC_H264_ENC 16
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#define S5P_FIMV_CODEC_MPEG4_ENC 17
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#define S5P_FIMV_CODEC_H263_ENC 18
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/* Channel Control Register */
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#define S5P_FIMV_CH_SEQ_HEADER 1
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#define S5P_FIMV_CH_FRAME_START 2
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#define S5P_FIMV_CH_LAST_FRAME 3
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#define S5P_FIMV_CH_INIT_BUFS 4
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#define S5P_FIMV_CH_FRAME_START_REALLOC 5
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#define S5P_FIMV_CH_MASK 7
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#define S5P_FIMV_CH_SHIFT 16
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/* Host to RISC command */
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#define S5P_FIMV_H2R_CMD_EMPTY 0
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#define S5P_FIMV_H2R_CMD_OPEN_INSTANCE 1
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#define S5P_FIMV_H2R_CMD_CLOSE_INSTANCE 2
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#define S5P_FIMV_H2R_CMD_SYS_INIT 3
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#define S5P_FIMV_H2R_CMD_FLUSH 4
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#define S5P_FIMV_H2R_CMD_SLEEP 5
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#define S5P_FIMV_H2R_CMD_WAKEUP 6
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#define S5P_FIMV_R2H_CMD_EMPTY 0
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#define S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET 1
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#define S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET 2
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#define S5P_FIMV_R2H_CMD_RSV_RET 3
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#define S5P_FIMV_R2H_CMD_SEQ_DONE_RET 4
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#define S5P_FIMV_R2H_CMD_FRAME_DONE_RET 5
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#define S5P_FIMV_R2H_CMD_SLICE_DONE_RET 6
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#define S5P_FIMV_R2H_CMD_ENC_COMPLETE_RET 7
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#define S5P_FIMV_R2H_CMD_SYS_INIT_RET 8
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#define S5P_FIMV_R2H_CMD_FW_STATUS_RET 9
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#define S5P_FIMV_R2H_CMD_SLEEP_RET 10
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#define S5P_FIMV_R2H_CMD_WAKEUP_RET 11
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#define S5P_FIMV_R2H_CMD_FLUSH_RET 12
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#define S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET 15
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#define S5P_FIMV_R2H_CMD_EDFU_INIT_RET 16
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#define S5P_FIMV_R2H_CMD_ERR_RET 32
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/* Dummy definition for MFCv6 compatibility */
|
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#define S5P_FIMV_CODEC_H264_MVC_DEC -1
|
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#define S5P_FIMV_R2H_CMD_FIELD_DONE_RET -1
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#define S5P_FIMV_MFC_RESET -1
|
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#define S5P_FIMV_RISC_ON -1
|
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#define S5P_FIMV_RISC_BASE_ADDRESS -1
|
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#define S5P_FIMV_CODEC_VP8_DEC -1
|
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#define S5P_FIMV_REG_CLEAR_BEGIN 0
|
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#define S5P_FIMV_REG_CLEAR_COUNT 0
|
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|
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/* Error handling defines */
|
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|
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#define S5P_FIMV_ERR_WARNINGS_START 145
|
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|
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#define S5P_FIMV_ERR_DEC_MASK 0xFFFF
|
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|
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#define S5P_FIMV_ERR_DEC_SHIFT 0
|
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|
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#define S5P_FIMV_ERR_DSPL_MASK 0xFFFF0000
|
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|
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#define S5P_FIMV_ERR_DSPL_SHIFT 16
|
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|
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|
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/* Shared memory registers' offsets */
|
||
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|
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|
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/* An offset of the start position in the stream when
|
||
|
|
* the start position is not aligned */
|
||
|
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#define S5P_FIMV_SHARED_CROP_INFO_H 0x0020
|
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|
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#define S5P_FIMV_SHARED_CROP_LEFT_MASK 0xFFFF
|
||
|
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#define S5P_FIMV_SHARED_CROP_LEFT_SHIFT 0
|
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|
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#define S5P_FIMV_SHARED_CROP_RIGHT_MASK 0xFFFF0000
|
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|
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#define S5P_FIMV_SHARED_CROP_RIGHT_SHIFT 16
|
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|
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#define S5P_FIMV_SHARED_CROP_INFO_V 0x0024
|
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|
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#define S5P_FIMV_SHARED_CROP_TOP_MASK 0xFFFF
|
||
|
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#define S5P_FIMV_SHARED_CROP_TOP_SHIFT 0
|
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|
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#define S5P_FIMV_SHARED_CROP_BOTTOM_MASK 0xFFFF0000
|
||
|
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#define S5P_FIMV_SHARED_CROP_BOTTOM_SHIFT 16
|
||
|
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#define S5P_FIMV_SHARED_SET_FRAME_TAG 0x0004
|
||
|
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#define S5P_FIMV_SHARED_GET_FRAME_TAG_TOP 0x0008
|
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|
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#define S5P_FIMV_SHARED_GET_FRAME_TAG_BOT 0x000C
|
||
|
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#define S5P_FIMV_SHARED_START_BYTE_NUM 0x0018
|
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|
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#define S5P_FIMV_SHARED_RC_VOP_TIMING 0x0030
|
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|
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#define S5P_FIMV_SHARED_LUMA_DPB_SIZE 0x0064
|
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|
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#define S5P_FIMV_SHARED_CHROMA_DPB_SIZE 0x0068
|
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|
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#define S5P_FIMV_SHARED_MV_SIZE 0x006C
|
||
|
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#define S5P_FIMV_SHARED_PIC_TIME_TOP 0x0010
|
||
|
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#define S5P_FIMV_SHARED_PIC_TIME_BOTTOM 0x0014
|
||
|
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#define S5P_FIMV_SHARED_EXT_ENC_CONTROL 0x0028
|
||
|
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#define S5P_FIMV_SHARED_P_B_FRAME_QP 0x0070
|
||
|
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#define S5P_FIMV_SHARED_ASPECT_RATIO_IDC 0x0074
|
||
|
|
#define S5P_FIMV_SHARED_EXTENDED_SAR 0x0078
|
||
|
|
#define S5P_FIMV_SHARED_H264_I_PERIOD 0x009C
|
||
|
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#define S5P_FIMV_SHARED_RC_CONTROL_CONFIG 0x00A0
|
||
|
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#define S5P_FIMV_SHARED_DISP_FRAME_TYPE_SHIFT 2
|
||
|
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|
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|
|
/* Offset used by the hardware to store addresses */
|
||
|
|
#define MFC_OFFSET_SHIFT 11
|
||
|
|
|
||
|
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#define FIRMWARE_ALIGN (128 * SZ_1K) /* 128KB */
|
||
|
|
#define MFC_H264_CTX_BUF_SIZE (600 * SZ_1K) /* 600KB per H264 instance */
|
||
|
|
#define MFC_CTX_BUF_SIZE (10 * SZ_1K) /* 10KB per instance */
|
||
|
|
#define DESC_BUF_SIZE (128 * SZ_1K) /* 128KB for DESC buffer */
|
||
|
|
#define SHARED_BUF_SIZE (8 * SZ_1K) /* 8KB for shared buffer */
|
||
|
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|
||
|
|
#define DEF_CPB_SIZE (256 * SZ_1K) /* 256KB */
|
||
|
|
#define MAX_CPB_SIZE (4 * SZ_1M) /* 4MB */
|
||
|
|
#define MAX_FW_SIZE (384 * SZ_1K)
|
||
|
|
|
||
|
|
#define MFC_VERSION 0x51
|
||
|
|
#define MFC_NUM_PORTS 2
|
||
|
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|
||
|
|
#define S5P_FIMV_SHARED_FRAME_PACK_SEI_AVAIL 0x16C
|
||
|
|
#define S5P_FIMV_SHARED_FRAME_PACK_ARRGMENT_ID 0x170
|
||
|
|
#define S5P_FIMV_SHARED_FRAME_PACK_SEI_INFO 0x174
|
||
|
|
#define S5P_FIMV_SHARED_FRAME_PACK_GRID_POS 0x178
|
||
|
|
|
||
|
|
/* Values for resolution change in display status */
|
||
|
|
#define S5P_FIMV_RES_INCREASE 1
|
||
|
|
#define S5P_FIMV_RES_DECREASE 2
|
||
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|
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|
|
#endif /* _REGS_FIMV_H */
|