188 lines
7.7 KiB
C
188 lines
7.7 KiB
C
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/*
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* Copyright (C) 2015 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __TEGRA210_MC_REG_H__
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#define __TEGRA210_MC_REG_H__
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#define MC_EMEM_ARB_MISC0 0xd8
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#define MC_TIMING_CONTROL 0xfc
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#define MC_AHB_PTSA_MIN 0x4e0
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#define MC_AUD_PTSA_MIN 0x54c
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#define MC_MLL_MPCORER_PTSA_RATE 0x44c
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#define MC_RING2_PTSA_RATE 0x440
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#define MC_USBD_PTSA_RATE 0x530
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#define MC_USBX_PTSA_MIN 0x528
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#define MC_USBD_PTSA_MIN 0x534
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#define MC_APB_PTSA_MAX 0x4f0
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#define MC_JPG_PTSA_RATE 0x584
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#define MC_DIS_PTSA_MIN 0x420
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#define MC_AVP_PTSA_MAX 0x4fc
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#define MC_AVP_PTSA_RATE 0x4f4
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#define MC_RING1_PTSA_MIN 0x480
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#define MC_DIS_PTSA_MAX 0x424
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#define MC_SD_PTSA_MAX 0x4d8
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#define MC_MSE_PTSA_RATE 0x4c4
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#define MC_VICPC_PTSA_MIN 0x558
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#define MC_PCX_PTSA_MAX 0x4b4
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#define MC_ISP_PTSA_RATE 0x4a0
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#define MC_A9AVPPC_PTSA_MIN 0x48c
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#define MC_RING2_PTSA_MAX 0x448
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#define MC_AUD_PTSA_RATE 0x548
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#define MC_HOST_PTSA_MIN 0x51c
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#define MC_MLL_MPCORER_PTSA_MAX 0x454
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#define MC_SD_PTSA_MIN 0x4d4
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#define MC_RING1_PTSA_RATE 0x47c
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#define MC_JPG_PTSA_MIN 0x588
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#define MC_HDAPC_PTSA_MIN 0x62c
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#define MC_AVP_PTSA_MIN 0x4f8
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#define MC_JPG_PTSA_MAX 0x58c
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#define MC_VE_PTSA_MAX 0x43c
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#define MC_DFD_PTSA_MAX 0x63c
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#define MC_VICPC_PTSA_RATE 0x554
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#define MC_GK_PTSA_MAX 0x544
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#define MC_VICPC_PTSA_MAX 0x55c
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#define MC_SDM_PTSA_MAX 0x624
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#define MC_SAX_PTSA_RATE 0x4b8
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#define MC_PCX_PTSA_MIN 0x4b0
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#define MC_APB_PTSA_MIN 0x4ec
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#define MC_GK2_PTSA_MIN 0x614
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#define MC_PCX_PTSA_RATE 0x4ac
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#define MC_RING1_PTSA_MAX 0x484
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#define MC_HDAPC_PTSA_RATE 0x628
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#define MC_MLL_MPCORER_PTSA_MIN 0x450
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#define MC_GK2_PTSA_MAX 0x618
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#define MC_AUD_PTSA_MAX 0x550
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#define MC_GK2_PTSA_RATE 0x610
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#define MC_ISP_PTSA_MAX 0x4a8
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#define MC_DISB_PTSA_RATE 0x428
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#define MC_VE2_PTSA_MAX 0x49c
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#define MC_DFD_PTSA_MIN 0x638
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#define MC_FTOP_PTSA_RATE 0x50c
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#define MC_A9AVPPC_PTSA_RATE 0x488
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#define MC_VE2_PTSA_MIN 0x498
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#define MC_USBX_PTSA_MAX 0x52c
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#define MC_DIS_PTSA_RATE 0x41c
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#define MC_USBD_PTSA_MAX 0x538
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#define MC_A9AVPPC_PTSA_MAX 0x490
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#define MC_USBX_PTSA_RATE 0x524
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#define MC_FTOP_PTSA_MAX 0x514
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#define MC_HDAPC_PTSA_MAX 0x630
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#define MC_SD_PTSA_RATE 0x4d0
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#define MC_DFD_PTSA_RATE 0x634
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#define MC_FTOP_PTSA_MIN 0x510
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#define MC_SDM_PTSA_RATE 0x61c
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#define MC_AHB_PTSA_RATE 0x4dc
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#define MC_SMMU_SMMU_PTSA_MAX 0x460
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#define MC_RING2_PTSA_MIN 0x444
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#define MC_SDM_PTSA_MIN 0x620
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#define MC_APB_PTSA_RATE 0x4e8
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#define MC_MSE_PTSA_MIN 0x4c8
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#define MC_HOST_PTSA_RATE 0x518
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#define MC_VE_PTSA_RATE 0x434
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#define MC_AHB_PTSA_MAX 0x4e4
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#define MC_SAX_PTSA_MIN 0x4bc
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#define MC_SMMU_SMMU_PTSA_MIN 0x45c
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#define MC_ISP_PTSA_MIN 0x4a4
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#define MC_HOST_PTSA_MAX 0x520
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#define MC_SAX_PTSA_MAX 0x4c0
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#define MC_VE_PTSA_MIN 0x438
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#define MC_GK_PTSA_MIN 0x540
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#define MC_MSE_PTSA_MAX 0x4cc
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#define MC_DISB_PTSA_MAX 0x430
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#define MC_DISB_PTSA_MIN 0x42c
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#define MC_SMMU_SMMU_PTSA_RATE 0x458
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#define MC_VE2_PTSA_RATE 0x494
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#define MC_GK_PTSA_RATE 0x53c
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#define MC_PTSA_GRANT_DECREMENT 0x960
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#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4
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#define MC_LATENCY_ALLOWANCE_AXIAP_0 0x3a0
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#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380
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#define MC_LATENCY_ALLOWANCE_ISP2B_0 0x384
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#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3bc
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#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3b8
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#define MC_LATENCY_ALLOWANCE_ISP2_0 0x370
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#define MC_LATENCY_ALLOWANCE_SE_0 0x3e0
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#define MC_LATENCY_ALLOWANCE_ISP2_1 0x374
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#define MC_LATENCY_ALLOWANCE_DC_0 0x2e8
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#define MC_LATENCY_ALLOWANCE_VIC_0 0x394
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#define MC_LATENCY_ALLOWANCE_DCB_1 0x2f8
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#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3d8
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#define MC_LATENCY_ALLOWANCE_DCB_2 0x2fc
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#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390
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#define MC_LATENCY_ALLOWANCE_DC_2 0x2f0
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB 0x694
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#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348
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#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c
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#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344
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#define MC_LATENCY_ALLOWANCE_TSECB_0 0x3f0
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#define MC_LATENCY_ALLOWANCE_AFI_0 0x2e0
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B 0x698
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#define MC_LATENCY_ALLOWANCE_DC_1 0x2ec
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#define MC_LATENCY_ALLOWANCE_APE_0 0x3dc
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C 0x6a0
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#define MC_LATENCY_ALLOWANCE_A9AVP_0 0x3a4
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#define MC_LATENCY_ALLOWANCE_GPU2_0 0x3e8
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#define MC_LATENCY_ALLOWANCE_DCB_0 0x2f4
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#define MC_LATENCY_ALLOWANCE_HC_1 0x314
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#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3c0
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#define MC_LATENCY_ALLOWANCE_NVJPG_0 0x3e4
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#define MC_LATENCY_ALLOWANCE_PTC_0 0x34c
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#define MC_LATENCY_ALLOWANCE_ETR_0 0x3ec
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#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
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#define MC_LATENCY_ALLOWANCE_VI2_0 0x398
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB 0x69c
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB 0x6a4
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#define MC_LATENCY_ALLOWANCE_SATA_0 0x350
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A 0x690
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#define MC_LATENCY_ALLOWANCE_HC_0 0x310
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#define MC_LATENCY_ALLOWANCE_DC_3 0x3c8
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#define MC_LATENCY_ALLOWANCE_GPU_0 0x3ac
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#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3c4
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#define MC_LATENCY_ALLOWANCE_ISP2B_1 0x388
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#define MC_LATENCY_ALLOWANCE_NVENC_0 0x328
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#define MC_LATENCY_ALLOWANCE_HDA_0 0x318
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_LOW_SHIFT 0
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_LOW_MASK \
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(0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_LOW_SHIFT)
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_HIGH_SHIFT 16
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_HIGH_MASK \
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(0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_HIGH_SHIFT)
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_LOW_SHIFT 0
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_LOW_MASK \
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(0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_LOW_SHIFT)
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_HIGH_SHIFT 16
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_HIGH_MASK \
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(0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_HIGH_SHIFT)
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_LOW_SHIFT 0
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_LOW_MASK \
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(0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_LOW_SHIFT)
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_HIGH_SHIFT 16
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_HIGH_MASK \
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(0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_HIGH_SHIFT)
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_LOW_SHIFT 0
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_LOW_MASK \
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(0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_LOW_SHIFT)
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_HIGH_SHIFT 16
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_HIGH_MASK \
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(0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_HIGH_SHIFT)
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_LOW_SHIFT 0
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_LOW_MASK \
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(0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_LOW_SHIFT)
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_HIGH_SHIFT 16
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_HIGH_MASK \
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(0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_HIGH_SHIFT)
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_LOW_SHIFT 0
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_LOW_MASK \
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(0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_LOW_SHIFT)
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_HIGH_SHIFT 16
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_HIGH_MASK \
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(0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_HIGH_SHIFT)
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#endif
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