434 lines
10 KiB
C
434 lines
10 KiB
C
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/*
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* Linux network driver for QLogic BR-series Converged Network Adapter.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License (GPL) Version 2 as
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* published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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/*
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* Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
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* Copyright (c) 2014-2015 QLogic Corporation
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* All rights reserved
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* www.qlogic.com
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*/
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#ifndef __BNAD_H__
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#define __BNAD_H__
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#include <linux/rtnetlink.h>
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#include <linux/workqueue.h>
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#include <linux/ipv6.h>
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#include <linux/etherdevice.h>
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#include <linux/mutex.h>
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#include <linux/firmware.h>
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#include <linux/if_vlan.h>
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/* Fix for IA64 */
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#include <asm/checksum.h>
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#include <net/ip6_checksum.h>
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#include <net/ip.h>
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#include <net/tcp.h>
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#include "bna.h"
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#define BNAD_TXQ_DEPTH 2048
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#define BNAD_RXQ_DEPTH 2048
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#define BNAD_MAX_TX 1
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#define BNAD_MAX_TXQ_PER_TX 8 /* 8 priority queues */
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#define BNAD_TXQ_NUM 1
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#define BNAD_MAX_RX 1
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#define BNAD_MAX_RXP_PER_RX 16
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#define BNAD_MAX_RXQ_PER_RXP 2
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/*
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* Control structure pointed to ccb->ctrl, which
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* determines the NAPI / LRO behavior CCB
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* There is 1:1 corres. between ccb & ctrl
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*/
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struct bnad_rx_ctrl {
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struct bna_ccb *ccb;
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struct bnad *bnad;
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unsigned long flags;
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struct napi_struct napi;
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u64 rx_intr_ctr;
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u64 rx_poll_ctr;
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u64 rx_schedule;
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u64 rx_keep_poll;
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u64 rx_complete;
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};
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#define BNAD_RXMODE_PROMISC_DEFAULT BNA_RXMODE_PROMISC
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/*
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* GLOBAL #defines (CONSTANTS)
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*/
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#define BNAD_NAME "bna"
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#define BNAD_NAME_LEN 64
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#define BNAD_VERSION "3.2.25.1"
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#define BNAD_MAILBOX_MSIX_INDEX 0
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#define BNAD_MAILBOX_MSIX_VECTORS 1
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#define BNAD_INTX_TX_IB_BITMASK 0x1
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#define BNAD_INTX_RX_IB_BITMASK 0x2
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#define BNAD_STATS_TIMER_FREQ 1000 /* in msecs */
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#define BNAD_DIM_TIMER_FREQ 1000 /* in msecs */
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#define BNAD_IOCETH_TIMEOUT 10000
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#define BNAD_MIN_Q_DEPTH 512
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#define BNAD_MAX_RXQ_DEPTH 16384
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#define BNAD_MAX_TXQ_DEPTH 2048
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#define BNAD_JUMBO_MTU 9000
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#define BNAD_NETIF_WAKE_THRESHOLD 8
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#define BNAD_RXQ_REFILL_THRESHOLD_SHIFT 3
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/* Bit positions for tcb->flags */
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#define BNAD_TXQ_FREE_SENT 0
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#define BNAD_TXQ_TX_STARTED 1
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/* Bit positions for rcb->flags */
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#define BNAD_RXQ_STARTED 0
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#define BNAD_RXQ_POST_OK 1
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/* Resource limits */
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#define BNAD_NUM_TXQ (bnad->num_tx * bnad->num_txq_per_tx)
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#define BNAD_NUM_RXP (bnad->num_rx * bnad->num_rxp_per_rx)
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#define BNAD_FRAME_SIZE(_mtu) \
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(ETH_HLEN + VLAN_HLEN + (_mtu) + ETH_FCS_LEN)
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/*
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* DATA STRUCTURES
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*/
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/* enums */
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enum bnad_intr_source {
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BNAD_INTR_TX = 1,
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BNAD_INTR_RX = 2
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};
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enum bnad_link_state {
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BNAD_LS_DOWN = 0,
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BNAD_LS_UP = 1
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};
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struct bnad_iocmd_comp {
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struct bnad *bnad;
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struct completion comp;
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int comp_status;
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};
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struct bnad_completion {
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struct completion ioc_comp;
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struct completion ucast_comp;
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struct completion mcast_comp;
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struct completion tx_comp;
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struct completion rx_comp;
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struct completion stats_comp;
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struct completion enet_comp;
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struct completion mtu_comp;
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u8 ioc_comp_status;
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u8 ucast_comp_status;
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u8 mcast_comp_status;
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u8 tx_comp_status;
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u8 rx_comp_status;
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u8 stats_comp_status;
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u8 port_comp_status;
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u8 mtu_comp_status;
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};
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/* Tx Rx Control Stats */
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struct bnad_drv_stats {
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u64 netif_queue_stop;
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u64 netif_queue_wakeup;
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u64 netif_queue_stopped;
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u64 tso4;
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u64 tso6;
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u64 tso_err;
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u64 tcpcsum_offload;
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u64 udpcsum_offload;
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u64 csum_help;
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u64 tx_skb_too_short;
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u64 tx_skb_stopping;
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u64 tx_skb_max_vectors;
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u64 tx_skb_mss_too_long;
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u64 tx_skb_tso_too_short;
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u64 tx_skb_tso_prepare;
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u64 tx_skb_non_tso_too_long;
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u64 tx_skb_tcp_hdr;
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u64 tx_skb_udp_hdr;
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u64 tx_skb_csum_err;
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u64 tx_skb_headlen_too_long;
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u64 tx_skb_headlen_zero;
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u64 tx_skb_frag_zero;
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u64 tx_skb_len_mismatch;
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u64 tx_skb_map_failed;
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u64 hw_stats_updates;
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u64 netif_rx_dropped;
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u64 link_toggle;
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u64 cee_toggle;
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u64 rxp_info_alloc_failed;
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u64 mbox_intr_disabled;
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u64 mbox_intr_enabled;
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u64 tx_unmap_q_alloc_failed;
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u64 rx_unmap_q_alloc_failed;
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u64 rxbuf_alloc_failed;
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u64 rxbuf_map_failed;
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};
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/* Complete driver stats */
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struct bnad_stats {
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struct bnad_drv_stats drv_stats;
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struct bna_stats *bna_stats;
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};
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/* Tx / Rx Resources */
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struct bnad_tx_res_info {
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struct bna_res_info res_info[BNA_TX_RES_T_MAX];
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};
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struct bnad_rx_res_info {
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struct bna_res_info res_info[BNA_RX_RES_T_MAX];
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};
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struct bnad_tx_info {
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struct bna_tx *tx; /* 1:1 between tx_info & tx */
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struct bna_tcb *tcb[BNAD_MAX_TXQ_PER_TX];
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u32 tx_id;
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struct delayed_work tx_cleanup_work;
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} ____cacheline_aligned;
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struct bnad_rx_info {
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struct bna_rx *rx; /* 1:1 between rx_info & rx */
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struct bnad_rx_ctrl rx_ctrl[BNAD_MAX_RXP_PER_RX];
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u32 rx_id;
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struct work_struct rx_cleanup_work;
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} ____cacheline_aligned;
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struct bnad_tx_vector {
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DEFINE_DMA_UNMAP_ADDR(dma_addr);
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DEFINE_DMA_UNMAP_LEN(dma_len);
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};
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struct bnad_tx_unmap {
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struct sk_buff *skb;
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u32 nvecs;
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struct bnad_tx_vector vectors[BFI_TX_MAX_VECTORS_PER_WI];
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};
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struct bnad_rx_vector {
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DEFINE_DMA_UNMAP_ADDR(dma_addr);
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u32 len;
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};
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struct bnad_rx_unmap {
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struct page *page;
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struct sk_buff *skb;
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struct bnad_rx_vector vector;
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u32 page_offset;
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};
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enum bnad_rxbuf_type {
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BNAD_RXBUF_NONE = 0,
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BNAD_RXBUF_SK_BUFF = 1,
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BNAD_RXBUF_PAGE = 2,
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BNAD_RXBUF_MULTI_BUFF = 3
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};
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#define BNAD_RXBUF_IS_SK_BUFF(_type) ((_type) == BNAD_RXBUF_SK_BUFF)
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#define BNAD_RXBUF_IS_MULTI_BUFF(_type) ((_type) == BNAD_RXBUF_MULTI_BUFF)
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struct bnad_rx_unmap_q {
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int reuse_pi;
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int alloc_order;
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u32 map_size;
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enum bnad_rxbuf_type type;
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struct bnad_rx_unmap unmap[0] ____cacheline_aligned;
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};
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#define BNAD_PCI_DEV_IS_CAT2(_bnad) \
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((_bnad)->pcidev->device == BFA_PCI_DEVICE_ID_CT2)
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/* Bit mask values for bnad->cfg_flags */
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#define BNAD_CF_DIM_ENABLED 0x01 /* DIM */
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#define BNAD_CF_PROMISC 0x02
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#define BNAD_CF_ALLMULTI 0x04
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#define BNAD_CF_DEFAULT 0x08
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#define BNAD_CF_MSIX 0x10 /* If in MSIx mode */
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/* Defines for run_flags bit-mask */
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/* Set, tested & cleared using xxx_bit() functions */
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/* Values indicated bit positions */
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#define BNAD_RF_CEE_RUNNING 0
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#define BNAD_RF_MTU_SET 1
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#define BNAD_RF_MBOX_IRQ_DISABLED 2
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#define BNAD_RF_NETDEV_REGISTERED 3
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#define BNAD_RF_DIM_TIMER_RUNNING 4
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#define BNAD_RF_STATS_TIMER_RUNNING 5
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#define BNAD_RF_TX_PRIO_SET 6
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struct bnad {
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struct net_device *netdev;
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u32 id;
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/* Data path */
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struct bnad_tx_info tx_info[BNAD_MAX_TX];
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struct bnad_rx_info rx_info[BNAD_MAX_RX];
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unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
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/*
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* These q numbers are global only because
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* they are used to calculate MSIx vectors.
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* Actually the exact # of queues are per Tx/Rx
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* object.
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*/
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u32 num_tx;
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u32 num_rx;
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u32 num_txq_per_tx;
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u32 num_rxp_per_rx;
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u32 txq_depth;
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u32 rxq_depth;
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u8 tx_coalescing_timeo;
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u8 rx_coalescing_timeo;
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struct bna_rx_config rx_config[BNAD_MAX_RX] ____cacheline_aligned;
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struct bna_tx_config tx_config[BNAD_MAX_TX] ____cacheline_aligned;
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void __iomem *bar0; /* BAR0 address */
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struct bna bna;
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u32 cfg_flags;
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unsigned long run_flags;
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struct pci_dev *pcidev;
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u64 mmio_start;
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u64 mmio_len;
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u32 msix_num;
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struct msix_entry *msix_table;
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struct mutex conf_mutex;
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spinlock_t bna_lock ____cacheline_aligned;
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/* Timers */
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struct timer_list ioc_timer;
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struct timer_list dim_timer;
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struct timer_list stats_timer;
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/* Control path resources, memory & irq */
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struct bna_res_info res_info[BNA_RES_T_MAX];
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struct bna_res_info mod_res_info[BNA_MOD_RES_T_MAX];
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struct bnad_tx_res_info tx_res_info[BNAD_MAX_TX];
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struct bnad_rx_res_info rx_res_info[BNAD_MAX_RX];
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struct bnad_completion bnad_completions;
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/* Burnt in MAC address */
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u8 perm_addr[ETH_ALEN];
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struct workqueue_struct *work_q;
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/* Statistics */
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struct bnad_stats stats;
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struct bnad_diag *diag;
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char adapter_name[BNAD_NAME_LEN];
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char port_name[BNAD_NAME_LEN];
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char mbox_irq_name[BNAD_NAME_LEN];
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char wq_name[BNAD_NAME_LEN];
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/* debugfs specific data */
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char *regdata;
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u32 reglen;
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struct dentry *bnad_dentry_files[5];
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struct dentry *port_debugfs_root;
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};
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struct bnad_drvinfo {
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struct bfa_ioc_attr ioc_attr;
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struct bfa_cee_attr cee_attr;
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struct bfa_flash_attr flash_attr;
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|
u32 cee_status;
|
||
|
|
u32 flash_status;
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* EXTERN VARIABLES
|
||
|
|
*/
|
||
|
|
extern const struct firmware *bfi_fw;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* EXTERN PROTOTYPES
|
||
|
|
*/
|
||
|
|
u32 *cna_get_firmware_buf(struct pci_dev *pdev);
|
||
|
|
/* Netdev entry point prototypes */
|
||
|
|
void bnad_set_rx_mode(struct net_device *netdev);
|
||
|
|
struct net_device_stats *bnad_get_netdev_stats(struct net_device *netdev);
|
||
|
|
int bnad_mac_addr_set_locked(struct bnad *bnad, const u8 *mac_addr);
|
||
|
|
int bnad_enable_default_bcast(struct bnad *bnad);
|
||
|
|
void bnad_restore_vlans(struct bnad *bnad, u32 rx_id);
|
||
|
|
void bnad_set_ethtool_ops(struct net_device *netdev);
|
||
|
|
void bnad_cb_completion(void *arg, enum bfa_status status);
|
||
|
|
|
||
|
|
/* Configuration & setup */
|
||
|
|
void bnad_tx_coalescing_timeo_set(struct bnad *bnad);
|
||
|
|
void bnad_rx_coalescing_timeo_set(struct bnad *bnad);
|
||
|
|
|
||
|
|
int bnad_setup_rx(struct bnad *bnad, u32 rx_id);
|
||
|
|
int bnad_setup_tx(struct bnad *bnad, u32 tx_id);
|
||
|
|
void bnad_destroy_tx(struct bnad *bnad, u32 tx_id);
|
||
|
|
void bnad_destroy_rx(struct bnad *bnad, u32 rx_id);
|
||
|
|
|
||
|
|
/* Timer start/stop protos */
|
||
|
|
void bnad_dim_timer_start(struct bnad *bnad);
|
||
|
|
|
||
|
|
/* Statistics */
|
||
|
|
void bnad_netdev_qstats_fill(struct bnad *bnad,
|
||
|
|
struct rtnl_link_stats64 *stats);
|
||
|
|
void bnad_netdev_hwstats_fill(struct bnad *bnad,
|
||
|
|
struct rtnl_link_stats64 *stats);
|
||
|
|
|
||
|
|
/* Debugfs */
|
||
|
|
void bnad_debugfs_init(struct bnad *bnad);
|
||
|
|
void bnad_debugfs_uninit(struct bnad *bnad);
|
||
|
|
|
||
|
|
/* MACROS */
|
||
|
|
/* To set & get the stats counters */
|
||
|
|
#define BNAD_UPDATE_CTR(_bnad, _ctr) \
|
||
|
|
(((_bnad)->stats.drv_stats._ctr)++)
|
||
|
|
|
||
|
|
#define BNAD_GET_CTR(_bnad, _ctr) ((_bnad)->stats.drv_stats._ctr)
|
||
|
|
|
||
|
|
#define bnad_enable_rx_irq_unsafe(_ccb) \
|
||
|
|
{ \
|
||
|
|
if (likely(test_bit(BNAD_RXQ_STARTED, &(_ccb)->rcb[0]->flags))) {\
|
||
|
|
bna_ib_coalescing_timer_set((_ccb)->i_dbell, \
|
||
|
|
(_ccb)->rx_coalescing_timeo); \
|
||
|
|
bna_ib_ack((_ccb)->i_dbell, 0); \
|
||
|
|
} \
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* __BNAD_H__ */
|