104 lines
3.7 KiB
C
104 lines
3.7 KiB
C
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/**********************************************************************
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* Author: Cavium, Inc.
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*
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* Contact: support@cavium.com
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* Please include "LiquidIO" in the subject.
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*
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* Copyright (c) 2003-2015 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium, Inc. for more information
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**********************************************************************/
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/*! \file cn66xx_device.h
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* \brief Host Driver: Routines that perform CN66XX specific operations.
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*/
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#ifndef __CN66XX_DEVICE_H__
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#define __CN66XX_DEVICE_H__
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/* Register address and configuration for a CN6XXX devices.
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* If device specific changes need to be made then add a struct to include
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* device specific fields as shown in the commented section
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*/
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struct octeon_cn6xxx {
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/** PCI interrupt summary register */
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u8 __iomem *intr_sum_reg64;
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/** PCI interrupt enable register */
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u8 __iomem *intr_enb_reg64;
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/** The PCI interrupt mask used by interrupt handler */
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u64 intr_mask64;
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struct octeon_config *conf;
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/* Example additional fields - not used currently
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* struct {
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* }cn6xyz;
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*/
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/* For the purpose of atomic access to interrupt enable reg */
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spinlock_t lock_for_droq_int_enb_reg;
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};
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enum octeon_pcie_mps {
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PCIE_MPS_DEFAULT = -1, /* Use the default setup by BIOS */
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PCIE_MPS_128B = 0,
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PCIE_MPS_256B = 1
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};
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enum octeon_pcie_mrrs {
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PCIE_MRRS_DEFAULT = -1, /* Use the default setup by BIOS */
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PCIE_MRRS_128B = 0,
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PCIE_MRRS_256B = 1,
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PCIE_MRRS_512B = 2,
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PCIE_MRRS_1024B = 3,
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PCIE_MRRS_2048B = 4,
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PCIE_MRRS_4096B = 5
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};
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/* Common functions for 66xx and 68xx */
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int lio_cn6xxx_soft_reset(struct octeon_device *oct);
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void lio_cn6xxx_enable_error_reporting(struct octeon_device *oct);
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void lio_cn6xxx_setup_pcie_mps(struct octeon_device *oct,
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enum octeon_pcie_mps mps);
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void lio_cn6xxx_setup_pcie_mrrs(struct octeon_device *oct,
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enum octeon_pcie_mrrs mrrs);
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void lio_cn6xxx_setup_global_input_regs(struct octeon_device *oct);
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void lio_cn6xxx_setup_global_output_regs(struct octeon_device *oct);
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void lio_cn6xxx_setup_iq_regs(struct octeon_device *oct, u32 iq_no);
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void lio_cn6xxx_setup_oq_regs(struct octeon_device *oct, u32 oq_no);
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int lio_cn6xxx_enable_io_queues(struct octeon_device *oct);
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void lio_cn6xxx_disable_io_queues(struct octeon_device *oct);
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irqreturn_t lio_cn6xxx_process_interrupt_regs(void *dev);
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void lio_cn6xxx_bar1_idx_setup(struct octeon_device *oct, u64 core_addr,
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u32 idx, int valid);
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void lio_cn6xxx_bar1_idx_write(struct octeon_device *oct, u32 idx, u32 mask);
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u32 lio_cn6xxx_bar1_idx_read(struct octeon_device *oct, u32 idx);
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u32
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lio_cn6xxx_update_read_index(struct octeon_instr_queue *iq);
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void lio_cn6xxx_enable_interrupt(struct octeon_device *oct, u8 unused);
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void lio_cn6xxx_disable_interrupt(struct octeon_device *oct, u8 unused);
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void cn6xxx_get_pcie_qlmport(struct octeon_device *oct);
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void lio_cn6xxx_setup_reg_address(struct octeon_device *oct, void *chip,
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struct octeon_reg_list *reg_list);
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u32 lio_cn6xxx_coprocessor_clock(struct octeon_device *oct);
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u32 lio_cn6xxx_get_oq_ticks(struct octeon_device *oct, u32 time_intr_in_us);
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int lio_setup_cn66xx_octeon_device(struct octeon_device *);
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int lio_validate_cn6xxx_config_info(struct octeon_device *oct,
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struct octeon_config *);
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#endif
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