470 lines
14 KiB
C
470 lines
14 KiB
C
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/**********************************************************************
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* Author: Cavium, Inc.
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*
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* Contact: support@cavium.com
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* Please include "LiquidIO" in the subject.
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*
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* Copyright (c) 2003-2015 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium, Inc. for more information
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**********************************************************************/
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/*! \file octeon_config.h
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* \brief Host Driver: Configuration data structures for the host driver.
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*/
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#ifndef __OCTEON_CONFIG_H__
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#define __OCTEON_CONFIG_H__
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/*--------------------------CONFIG VALUES------------------------*/
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/* The following macros affect the way the driver data structures
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* are generated for Octeon devices.
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* They can be modified.
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*/
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/* Maximum octeon devices defined as MAX_OCTEON_NICIF to support
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* multiple(<= MAX_OCTEON_NICIF) Miniports
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*/
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#define MAX_OCTEON_NICIF 128
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#define MAX_OCTEON_DEVICES MAX_OCTEON_NICIF
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#define MAX_OCTEON_LINKS MAX_OCTEON_NICIF
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#define MAX_OCTEON_MULTICAST_ADDR 32
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/* CN6xxx IQ configuration macros */
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#define CN6XXX_MAX_INPUT_QUEUES 32
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#define CN6XXX_MAX_IQ_DESCRIPTORS 2048
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#define CN6XXX_DB_MIN 1
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#define CN6XXX_DB_MAX 8
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#define CN6XXX_DB_TIMEOUT 1
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/* CN6xxx OQ configuration macros */
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#define CN6XXX_MAX_OUTPUT_QUEUES 32
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#define CN6XXX_MAX_OQ_DESCRIPTORS 2048
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#define CN6XXX_OQ_BUF_SIZE 1536
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#define CN6XXX_OQ_PKTSPER_INTR ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \
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(CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128)
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#define CN6XXX_OQ_REFIL_THRESHOLD ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \
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(CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128)
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#define CN6XXX_OQ_INTR_PKT 64
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#define CN6XXX_OQ_INTR_TIME 100
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#define DEFAULT_NUM_NIC_PORTS_66XX 2
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#define DEFAULT_NUM_NIC_PORTS_68XX 4
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#define DEFAULT_NUM_NIC_PORTS_68XX_210NV 2
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/* CN23xx IQ configuration macros */
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#define CN23XX_MAX_RINGS_PER_PF_PASS_1_0 12
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#define CN23XX_MAX_RINGS_PER_PF_PASS_1_1 32
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#define CN23XX_MAX_RINGS_PER_PF 64
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#define CN23XX_MAX_INPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
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#define CN23XX_MAX_IQ_DESCRIPTORS 2048
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#define CN23XX_DB_MIN 1
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#define CN23XX_DB_MAX 8
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#define CN23XX_DB_TIMEOUT 1
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#define CN23XX_MAX_OUTPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
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#define CN23XX_MAX_OQ_DESCRIPTORS 2048
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#define CN23XX_OQ_BUF_SIZE 1536
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#define CN23XX_OQ_PKTSPER_INTR 128
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/*#define CAVIUM_ONLY_CN23XX_RX_PERF*/
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#define CN23XX_OQ_REFIL_THRESHOLD 128
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#define CN23XX_OQ_INTR_PKT 64
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#define CN23XX_OQ_INTR_TIME 100
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#define DEFAULT_NUM_NIC_PORTS_23XX 1
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#define CN23XX_CFG_IO_QUEUES CN23XX_MAX_RINGS_PER_PF
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/* PEMs count */
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#define CN23XX_MAX_MACS 4
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#define CN23XX_DEF_IQ_INTR_THRESHOLD 32
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#define CN23XX_DEF_IQ_INTR_BYTE_THRESHOLD (64 * 1024)
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/* common OCTEON configuration macros */
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#define CN6XXX_CFG_IO_QUEUES 32
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#define OCTEON_32BYTE_INSTR 32
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#define OCTEON_64BYTE_INSTR 64
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#define OCTEON_MAX_BASE_IOQ 4
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#define OCTEON_OQ_BUFPTR_MODE 0
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#define OCTEON_OQ_INFOPTR_MODE 1
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#define OCTEON_DMA_INTR_PKT 64
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#define OCTEON_DMA_INTR_TIME 1000
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#define MAX_TXQS_PER_INTF 8
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#define MAX_RXQS_PER_INTF 8
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#define DEF_TXQS_PER_INTF 4
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#define DEF_RXQS_PER_INTF 4
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#define INVALID_IOQ_NO 0xff
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#define DEFAULT_POW_GRP 0
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/* Macros to get octeon config params */
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#define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
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#define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs)
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#define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size)
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#define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
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#define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
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#define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout)
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#define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt)
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#define CFG_SET_IQ_INTR_PKT(cfg, val) (cfg)->iq.iq_intr_pkt = val
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#define CFG_GET_OQ_MAX_Q(cfg) ((cfg)->oq.max_oqs)
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#define CFG_GET_OQ_INFO_PTR(cfg) ((cfg)->oq.info_ptr)
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#define CFG_GET_OQ_PKTS_PER_INTR(cfg) ((cfg)->oq.pkts_per_intr)
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#define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold)
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#define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt)
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#define CFG_GET_OQ_INTR_TIME(cfg) ((cfg)->oq.oq_intr_time)
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#define CFG_SET_OQ_INTR_PKT(cfg, val) (cfg)->oq.oq_intr_pkt = val
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#define CFG_SET_OQ_INTR_TIME(cfg, val) (cfg)->oq.oq_intr_time = val
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#define CFG_GET_DMA_INTR_PKT(cfg) ((cfg)->dma.dma_intr_pkt)
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#define CFG_GET_DMA_INTR_TIME(cfg) ((cfg)->dma.dma_intr_time)
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#define CFG_GET_NUM_NIC_PORTS(cfg) ((cfg)->num_nic_ports)
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#define CFG_GET_NUM_DEF_TX_DESCS(cfg) ((cfg)->num_def_tx_descs)
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#define CFG_GET_NUM_DEF_RX_DESCS(cfg) ((cfg)->num_def_rx_descs)
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#define CFG_GET_DEF_RX_BUF_SIZE(cfg) ((cfg)->def_rx_buf_size)
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#define CFG_GET_MAX_TXQS_NIC_IF(cfg, idx) \
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((cfg)->nic_if_cfg[idx].max_txqs)
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#define CFG_GET_NUM_TXQS_NIC_IF(cfg, idx) \
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((cfg)->nic_if_cfg[idx].num_txqs)
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#define CFG_GET_MAX_RXQS_NIC_IF(cfg, idx) \
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((cfg)->nic_if_cfg[idx].max_rxqs)
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#define CFG_GET_NUM_RXQS_NIC_IF(cfg, idx) \
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((cfg)->nic_if_cfg[idx].num_rxqs)
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#define CFG_GET_NUM_RX_DESCS_NIC_IF(cfg, idx) \
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((cfg)->nic_if_cfg[idx].num_rx_descs)
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#define CFG_GET_NUM_TX_DESCS_NIC_IF(cfg, idx) \
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((cfg)->nic_if_cfg[idx].num_tx_descs)
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#define CFG_GET_NUM_RX_BUF_SIZE_NIC_IF(cfg, idx) \
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((cfg)->nic_if_cfg[idx].rx_buf_size)
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#define CFG_GET_BASE_QUE_NIC_IF(cfg, idx) \
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((cfg)->nic_if_cfg[idx].base_queue)
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#define CFG_GET_GMXID_NIC_IF(cfg, idx) \
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((cfg)->nic_if_cfg[idx].gmx_port_id)
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#define CFG_GET_CTRL_Q_GRP(cfg) ((cfg)->misc.ctrlq_grp)
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#define CFG_GET_HOST_LINK_QUERY_INTERVAL(cfg) \
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((cfg)->misc.host_link_query_interval)
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#define CFG_GET_OCT_LINK_QUERY_INTERVAL(cfg) \
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((cfg)->misc.oct_link_query_interval)
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#define CFG_GET_IS_SLI_BP_ON(cfg) ((cfg)->misc.enable_sli_oq_bp)
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/* Max IOQs per OCTEON Link */
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#define MAX_IOQS_PER_NICIF 64
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enum lio_card_type {
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LIO_210SV = 0, /* Two port, 66xx */
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LIO_210NV, /* Two port, 68xx */
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LIO_410NV, /* Four port, 68xx */
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LIO_23XX /* 23xx */
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};
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#define LIO_210SV_NAME "210sv"
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#define LIO_210NV_NAME "210nv"
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#define LIO_410NV_NAME "410nv"
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#define LIO_23XX_NAME "23xx"
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/** Structure to define the configuration attributes for each Input queue.
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* Applicable to all Octeon processors
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**/
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struct octeon_iq_config {
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#ifdef __BIG_ENDIAN_BITFIELD
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u64 reserved:16;
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/** Tx interrupt packets. Applicable to 23xx only */
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u64 iq_intr_pkt:16;
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/** Minimum ticks to wait before checking for pending instructions. */
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u64 db_timeout:16;
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/** Minimum number of commands pending to be posted to Octeon
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* before driver hits the Input queue doorbell.
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*/
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u64 db_min:8;
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/** Command size - 32 or 64 bytes */
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u64 instr_type:32;
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/** Pending list size (usually set to the sum of the size of all Input
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* queues)
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*/
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u64 pending_list_size:32;
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/* Max number of IQs available */
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u64 max_iqs:8;
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#else
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/* Max number of IQs available */
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u64 max_iqs:8;
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/** Pending list size (usually set to the sum of the size of all Input
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* queues)
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*/
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u64 pending_list_size:32;
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/** Command size - 32 or 64 bytes */
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u64 instr_type:32;
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/** Minimum number of commands pending to be posted to Octeon
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* before driver hits the Input queue doorbell.
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*/
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u64 db_min:8;
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/** Minimum ticks to wait before checking for pending instructions. */
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u64 db_timeout:16;
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/** Tx interrupt packets. Applicable to 23xx only */
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u64 iq_intr_pkt:16;
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u64 reserved:16;
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#endif
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};
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/** Structure to define the configuration attributes for each Output queue.
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* Applicable to all Octeon processors
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**/
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struct octeon_oq_config {
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#ifdef __BIG_ENDIAN_BITFIELD
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u64 reserved:16;
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u64 pkts_per_intr:16;
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/** Interrupt Coalescing (Time Interval). Octeon will interrupt the
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* host if atleast one packet was sent in the time interval specified
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* by this field. The driver uses time interval interrupt coalescing
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* by default. The time is specified in microseconds.
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*/
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u64 oq_intr_time:16;
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/** Interrupt Coalescing (Packet Count). Octeon will interrupt the host
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* only if it sent as many packets as specified by this field.
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* The driver
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* usually does not use packet count interrupt coalescing.
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*/
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u64 oq_intr_pkt:16;
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/** The number of buffers that were consumed during packet processing by
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* the driver on this Output queue before the driver attempts to
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* replenish
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* the descriptor ring with new buffers.
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*/
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u64 refill_threshold:16;
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/** If set, the Output queue uses info-pointer mode. (Default: 1) */
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u64 info_ptr:32;
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/* Max number of OQs available */
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u64 max_oqs:8;
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#else
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/* Max number of OQs available */
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u64 max_oqs:8;
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/** If set, the Output queue uses info-pointer mode. (Default: 1) */
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u64 info_ptr:32;
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/** The number of buffers that were consumed during packet processing by
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* the driver on this Output queue before the driver attempts to
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* replenish
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* the descriptor ring with new buffers.
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*/
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u64 refill_threshold:16;
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/** Interrupt Coalescing (Packet Count). Octeon will interrupt the host
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* only if it sent as many packets as specified by this field.
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* The driver
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* usually does not use packet count interrupt coalescing.
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*/
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u64 oq_intr_pkt:16;
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/** Interrupt Coalescing (Time Interval). Octeon will interrupt the
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* host if atleast one packet was sent in the time interval specified
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* by this field. The driver uses time interval interrupt coalescing
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* by default. The time is specified in microseconds.
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*/
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u64 oq_intr_time:16;
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u64 pkts_per_intr:16;
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u64 reserved:16;
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#endif
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};
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/** This structure conatins the NIC link configuration attributes,
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* common for all the OCTEON Modles.
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*/
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struct octeon_nic_if_config {
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#ifdef __BIG_ENDIAN_BITFIELD
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u64 reserved:56;
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u64 base_queue:16;
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u64 gmx_port_id:8;
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/* SKB size, We need not change buf size even for Jumbo frames.
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* Octeon can send jumbo frames in 4 consecutive descriptors,
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*/
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u64 rx_buf_size:16;
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/* Num of desc for tx rings */
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u64 num_tx_descs:16;
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/* Num of desc for rx rings */
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u64 num_rx_descs:16;
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/* Actual configured value. Range could be: 1...max_rxqs */
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u64 num_rxqs:16;
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/* Max Rxqs: Half for each of the two ports :max_oq/2 */
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u64 max_rxqs:16;
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/* Actual configured value. Range could be: 1...max_txqs */
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u64 num_txqs:16;
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/* Max Txqs: Half for each of the two ports :max_iq/2 */
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||
|
|
u64 max_txqs:16;
|
||
|
|
#else
|
||
|
|
/* Max Txqs: Half for each of the two ports :max_iq/2 */
|
||
|
|
u64 max_txqs:16;
|
||
|
|
|
||
|
|
/* Actual configured value. Range could be: 1...max_txqs */
|
||
|
|
u64 num_txqs:16;
|
||
|
|
|
||
|
|
/* Max Rxqs: Half for each of the two ports :max_oq/2 */
|
||
|
|
u64 max_rxqs:16;
|
||
|
|
|
||
|
|
/* Actual configured value. Range could be: 1...max_rxqs */
|
||
|
|
u64 num_rxqs:16;
|
||
|
|
|
||
|
|
/* Num of desc for rx rings */
|
||
|
|
u64 num_rx_descs:16;
|
||
|
|
|
||
|
|
/* Num of desc for tx rings */
|
||
|
|
u64 num_tx_descs:16;
|
||
|
|
|
||
|
|
/* SKB size, We need not change buf size even for Jumbo frames.
|
||
|
|
* Octeon can send jumbo frames in 4 consecutive descriptors,
|
||
|
|
*/
|
||
|
|
u64 rx_buf_size:16;
|
||
|
|
|
||
|
|
u64 gmx_port_id:8;
|
||
|
|
|
||
|
|
u64 base_queue:16;
|
||
|
|
|
||
|
|
u64 reserved:56;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
};
|
||
|
|
|
||
|
|
/** Structure to define the configuration attributes for meta data.
|
||
|
|
* Applicable to all Octeon processors.
|
||
|
|
*/
|
||
|
|
|
||
|
|
struct octeon_misc_config {
|
||
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
||
|
|
/** Host link status polling period */
|
||
|
|
u64 host_link_query_interval:32;
|
||
|
|
/** Oct link status polling period */
|
||
|
|
u64 oct_link_query_interval:32;
|
||
|
|
|
||
|
|
u64 enable_sli_oq_bp:1;
|
||
|
|
/** Control IQ Group */
|
||
|
|
u64 ctrlq_grp:4;
|
||
|
|
#else
|
||
|
|
/** Control IQ Group */
|
||
|
|
u64 ctrlq_grp:4;
|
||
|
|
/** BP for SLI OQ */
|
||
|
|
u64 enable_sli_oq_bp:1;
|
||
|
|
/** Host link status polling period */
|
||
|
|
u64 oct_link_query_interval:32;
|
||
|
|
/** Oct link status polling period */
|
||
|
|
u64 host_link_query_interval:32;
|
||
|
|
#endif
|
||
|
|
};
|
||
|
|
|
||
|
|
/** Structure to define the configuration for all OCTEON processors. */
|
||
|
|
struct octeon_config {
|
||
|
|
u16 card_type;
|
||
|
|
char *card_name;
|
||
|
|
|
||
|
|
/** Input Queue attributes. */
|
||
|
|
struct octeon_iq_config iq;
|
||
|
|
|
||
|
|
/** Output Queue attributes. */
|
||
|
|
struct octeon_oq_config oq;
|
||
|
|
|
||
|
|
/** NIC Port Configuration */
|
||
|
|
struct octeon_nic_if_config nic_if_cfg[MAX_OCTEON_NICIF];
|
||
|
|
|
||
|
|
/** Miscellaneous attributes */
|
||
|
|
struct octeon_misc_config misc;
|
||
|
|
|
||
|
|
int num_nic_ports;
|
||
|
|
|
||
|
|
int num_def_tx_descs;
|
||
|
|
|
||
|
|
/* Num of desc for rx rings */
|
||
|
|
int num_def_rx_descs;
|
||
|
|
|
||
|
|
int def_rx_buf_size;
|
||
|
|
|
||
|
|
};
|
||
|
|
|
||
|
|
/* The following config values are fixed and should not be modified. */
|
||
|
|
|
||
|
|
/* Maximum address space to be mapped for Octeon's BAR1 index-based access. */
|
||
|
|
#define MAX_BAR1_MAP_INDEX 2
|
||
|
|
#define OCTEON_BAR1_ENTRY_SIZE (4 * 1024 * 1024)
|
||
|
|
|
||
|
|
/* BAR1 Index 0 to (MAX_BAR1_MAP_INDEX - 1) for normal mapped memory access.
|
||
|
|
* Bar1 register at MAX_BAR1_MAP_INDEX used by driver for dynamic access.
|
||
|
|
*/
|
||
|
|
#define MAX_BAR1_IOREMAP_SIZE ((MAX_BAR1_MAP_INDEX + 1) * \
|
||
|
|
OCTEON_BAR1_ENTRY_SIZE)
|
||
|
|
|
||
|
|
/* Response lists - 1 ordered, 1 unordered-blocking, 1 unordered-nonblocking
|
||
|
|
* NoResponse Lists are now maintained with each IQ. (Dec' 2007).
|
||
|
|
*/
|
||
|
|
#define MAX_RESPONSE_LISTS 4
|
||
|
|
|
||
|
|
/* Opcode hash bits. The opcode is hashed on the lower 6-bits to lookup the
|
||
|
|
* dispatch table.
|
||
|
|
*/
|
||
|
|
#define OPCODE_MASK_BITS 6
|
||
|
|
|
||
|
|
/* Mask for the 6-bit lookup hash */
|
||
|
|
#define OCTEON_OPCODE_MASK 0x3f
|
||
|
|
|
||
|
|
/* Size of the dispatch table. The 6-bit hash can index into 2^6 entries */
|
||
|
|
#define DISPATCH_LIST_SIZE BIT(OPCODE_MASK_BITS)
|
||
|
|
|
||
|
|
/* Maximum number of Octeon Instruction (command) queues */
|
||
|
|
#define MAX_OCTEON_INSTR_QUEUES(oct) \
|
||
|
|
(OCTEON_CN23XX_PF(oct) ? CN23XX_MAX_INPUT_QUEUES : \
|
||
|
|
CN6XXX_MAX_INPUT_QUEUES)
|
||
|
|
|
||
|
|
/* Maximum number of Octeon Instruction (command) queues */
|
||
|
|
#define MAX_OCTEON_OUTPUT_QUEUES(oct) \
|
||
|
|
(OCTEON_CN23XX_PF(oct) ? CN23XX_MAX_OUTPUT_QUEUES : \
|
||
|
|
CN6XXX_MAX_OUTPUT_QUEUES)
|
||
|
|
|
||
|
|
#define MAX_POSSIBLE_OCTEON_INSTR_QUEUES CN23XX_MAX_INPUT_QUEUES
|
||
|
|
#define MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES CN23XX_MAX_OUTPUT_QUEUES
|
||
|
|
#endif /* __OCTEON_CONFIG_H__ */
|