214 lines
9.9 KiB
C
214 lines
9.9 KiB
C
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/*******************************************************************************
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Intel(R) 10GbE PCI Express Linux Network Driver
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Copyright(c) 1999 - 2017 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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Linux NICS <linux.nics@intel.com>
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#ifndef _IXGBE_API_H_
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#define _IXGBE_API_H_
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#include "ixgbe_type.h"
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void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map);
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s32 ixgbe_init_shared_code(struct ixgbe_hw *hw);
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extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
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extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);
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extern s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw);
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extern s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw);
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extern s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw);
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extern s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw);
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extern s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw);
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s32 ixgbe_set_mac_type(struct ixgbe_hw *hw);
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s32 ixgbe_init_hw(struct ixgbe_hw *hw);
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s32 ixgbe_reset_hw(struct ixgbe_hw *hw);
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s32 ixgbe_start_hw(struct ixgbe_hw *hw);
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s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw);
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enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw);
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s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr);
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s32 ixgbe_get_bus_info(struct ixgbe_hw *hw);
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u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw);
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u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw);
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s32 ixgbe_stop_adapter(struct ixgbe_hw *hw);
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s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size);
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s32 ixgbe_identify_phy(struct ixgbe_hw *hw);
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s32 ixgbe_reset_phy(struct ixgbe_hw *hw);
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s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
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u16 *phy_data);
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s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
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u16 phy_data);
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s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw);
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s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw);
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s32 ixgbe_check_phy_link(struct ixgbe_hw *hw,
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ixgbe_link_speed *speed,
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bool *link_up);
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s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw,
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ixgbe_link_speed speed,
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bool autoneg_wait_to_complete);
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s32 ixgbe_set_phy_power(struct ixgbe_hw *, bool on);
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void ixgbe_disable_tx_laser(struct ixgbe_hw *hw);
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void ixgbe_enable_tx_laser(struct ixgbe_hw *hw);
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void ixgbe_flap_tx_laser(struct ixgbe_hw *hw);
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s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
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bool autoneg_wait_to_complete);
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s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
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bool autoneg_wait_to_complete);
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s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
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bool *link_up, bool link_up_wait_to_complete);
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s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
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bool *autoneg);
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s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index);
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s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index);
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s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index);
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s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index);
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s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw);
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s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data);
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s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
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u16 words, u16 *data);
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s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data);
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s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
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u16 words, u16 *data);
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s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val);
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s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw);
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s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
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s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
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u32 enable_addr);
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s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index);
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s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
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s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq);
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s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
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s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw);
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u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw);
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s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
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u32 addr_count, ixgbe_mc_addr_itr func);
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s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
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u32 mc_addr_count, ixgbe_mc_addr_itr func,
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bool clear);
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void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr_list, u32 vmdq);
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s32 ixgbe_enable_mc(struct ixgbe_hw *hw);
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s32 ixgbe_disable_mc(struct ixgbe_hw *hw);
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s32 ixgbe_clear_vfta(struct ixgbe_hw *hw);
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s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan,
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u32 vind, bool vlan_on, bool vlvf_bypass);
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s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind,
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bool vlan_on, u32 *vfta_delta, u32 vfta,
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bool vlvf_bypass);
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s32 ixgbe_fc_enable(struct ixgbe_hw *hw);
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s32 ixgbe_setup_fc(struct ixgbe_hw *hw);
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s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
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u8 ver, u16 len, char *driver_ver);
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s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw);
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s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw);
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void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr);
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s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw,
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u16 *firmware_version);
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s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);
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s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);
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s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw);
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s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data);
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u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw);
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s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval);
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s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw);
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s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw);
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s32 ixgbe_mng_fw_enabled(struct ixgbe_hw *hw);
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s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
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s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
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s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
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bool cloud_mode);
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void ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_hash_dword input,
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union ixgbe_atr_hash_dword common,
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u8 queue);
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s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_input *input_mask, bool cloud_mode);
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s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_input *input,
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u16 soft_id, u8 queue, bool cloud_mode);
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s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_input *input,
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u16 soft_id);
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s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_input *input,
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union ixgbe_atr_input *mask,
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u16 soft_id,
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u8 queue,
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bool cloud_mode);
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void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
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union ixgbe_atr_input *mask);
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u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
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union ixgbe_atr_hash_dword common);
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bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
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s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
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u8 *data);
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s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
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u8 dev_addr, u8 *data);
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s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val);
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s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val);
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s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
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u8 data);
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void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue);
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s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
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u8 dev_addr, u8 data);
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s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val);
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s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val);
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s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data);
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s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
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s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
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s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps);
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s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask);
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void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask);
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void ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw);
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s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
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u16 *wwpn_prefix);
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s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs);
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s32 ixgbe_dmac_config(struct ixgbe_hw *hw);
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s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw);
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s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw);
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s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee);
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void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable,
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unsigned int vf);
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void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable,
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int vf);
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s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
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u32 device_type, u32 *phy_data);
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s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
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u32 device_type, u32 phy_data);
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void ixgbe_disable_mdd(struct ixgbe_hw *hw);
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void ixgbe_enable_mdd(struct ixgbe_hw *hw);
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void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap);
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void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf);
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s32 ixgbe_enter_lplu(struct ixgbe_hw *hw);
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s32 ixgbe_handle_lasi(struct ixgbe_hw *hw);
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void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed);
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void ixgbe_disable_rx(struct ixgbe_hw *hw);
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void ixgbe_enable_rx(struct ixgbe_hw *hw);
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s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
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u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
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#endif /* _IXGBE_API_H_ */
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