76 lines
2.9 KiB
C
76 lines
2.9 KiB
C
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/*
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* drivers/net/ethernet/mellanox/mlxsw/trap.h
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* Copyright (c) 2015 Mellanox Technologies. All rights reserved.
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* Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
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* Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
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* Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the names of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MLXSW_TRAP_H
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#define _MLXSW_TRAP_H
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enum {
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/* Ethernet EMAD and FDB miss */
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MLXSW_TRAP_ID_FDB_MC = 0x01,
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MLXSW_TRAP_ID_ETHEMAD = 0x05,
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/* L2 traps for specific packet types */
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MLXSW_TRAP_ID_STP = 0x10,
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MLXSW_TRAP_ID_LACP = 0x11,
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MLXSW_TRAP_ID_EAPOL = 0x12,
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MLXSW_TRAP_ID_LLDP = 0x13,
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MLXSW_TRAP_ID_MMRP = 0x14,
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MLXSW_TRAP_ID_MVRP = 0x15,
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MLXSW_TRAP_ID_RPVST = 0x16,
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MLXSW_TRAP_ID_DHCP = 0x19,
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MLXSW_TRAP_ID_IGMP_QUERY = 0x30,
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MLXSW_TRAP_ID_IGMP_V1_REPORT = 0x31,
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MLXSW_TRAP_ID_IGMP_V2_REPORT = 0x32,
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MLXSW_TRAP_ID_IGMP_V2_LEAVE = 0x33,
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MLXSW_TRAP_ID_IGMP_V3_REPORT = 0x34,
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MLXSW_TRAP_ID_ARPBC = 0x50,
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MLXSW_TRAP_ID_ARPUC = 0x51,
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MLXSW_TRAP_ID_MTUERROR = 0x52,
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MLXSW_TRAP_ID_TTLERROR = 0x53,
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MLXSW_TRAP_ID_LBERROR = 0x54,
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MLXSW_TRAP_ID_OSPF = 0x55,
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MLXSW_TRAP_ID_IP2ME = 0x5F,
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MLXSW_TRAP_ID_RTR_INGRESS0 = 0x70,
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MLXSW_TRAP_ID_HOST_MISS_IPV4 = 0x90,
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MLXSW_TRAP_ID_MAX = 0x1FF
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};
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enum mlxsw_event_trap_id {
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/* Port Up/Down event generated by hardware */
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MLXSW_TRAP_ID_PUDE = 0x8,
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};
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#endif /* _MLXSW_TRAP_H */
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