357 lines
11 KiB
C
357 lines
11 KiB
C
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/*
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* This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
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* DWC Ether MAC version 4.xx has been used for developing this code.
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*
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* This contains the functions to handle the dma.
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*
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* Copyright (C) 2015 STMicroelectronics Ltd
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* Author: Alexandre Torgue <alexandre.torgue@st.com>
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*/
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#include <linux/io.h>
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#include "dwmac4.h"
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#include "dwmac4_dma.h"
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static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
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{
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u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
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int i;
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pr_info("dwmac4: Master AXI performs %s burst length\n",
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(value & DMA_SYS_BUS_FB) ? "fixed" : "any");
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if (axi->axi_lpi_en)
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value |= DMA_AXI_EN_LPI;
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if (axi->axi_xit_frm)
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value |= DMA_AXI_LPI_XIT_FRM;
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value &= ~DMA_AXI_WR_OSR_LMT;
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value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) <<
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DMA_AXI_WR_OSR_LMT_SHIFT;
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value &= ~DMA_AXI_RD_OSR_LMT;
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value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) <<
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DMA_AXI_RD_OSR_LMT_SHIFT;
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/* Depending on the UNDEF bit the Master AXI will perform any burst
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* length according to the BLEN programmed (by default all BLEN are
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* set).
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*/
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for (i = 0; i < AXI_BLEN; i++) {
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switch (axi->axi_blen[i]) {
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case 256:
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value |= DMA_AXI_BLEN256;
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break;
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case 128:
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value |= DMA_AXI_BLEN128;
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break;
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case 64:
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value |= DMA_AXI_BLEN64;
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break;
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case 32:
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value |= DMA_AXI_BLEN32;
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break;
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case 16:
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value |= DMA_AXI_BLEN16;
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break;
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case 8:
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value |= DMA_AXI_BLEN8;
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break;
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case 4:
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value |= DMA_AXI_BLEN4;
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break;
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}
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}
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writel(value, ioaddr + DMA_SYS_BUS_MODE);
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}
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static void dwmac4_dma_init_channel(void __iomem *ioaddr, int pbl,
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u32 dma_tx_phy, u32 dma_rx_phy,
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u32 channel)
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{
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u32 value;
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/* set PBL for each channels. Currently we affect same configuration
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* on each channel
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*/
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value = readl(ioaddr + DMA_CHAN_CONTROL(channel));
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value = value | DMA_BUS_MODE_PBL;
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writel(value, ioaddr + DMA_CHAN_CONTROL(channel));
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value = readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));
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value = value | (pbl << DMA_BUS_MODE_PBL_SHIFT);
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writel(value, ioaddr + DMA_CHAN_TX_CONTROL(channel));
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value = readl(ioaddr + DMA_CHAN_RX_CONTROL(channel));
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value = value | (pbl << DMA_BUS_MODE_RPBL_SHIFT);
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writel(value, ioaddr + DMA_CHAN_RX_CONTROL(channel));
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/* Mask interrupts by writing to CSR7 */
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writel(DMA_CHAN_INTR_DEFAULT_MASK, ioaddr + DMA_CHAN_INTR_ENA(channel));
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writel(dma_tx_phy, ioaddr + DMA_CHAN_TX_BASE_ADDR(channel));
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writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));
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}
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static void dwmac4_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb,
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int aal, u32 dma_tx, u32 dma_rx, int atds)
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{
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u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
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int i;
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/* Set the Fixed burst mode */
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if (fb)
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value |= DMA_SYS_BUS_FB;
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/* Mixed Burst has no effect when fb is set */
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if (mb)
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value |= DMA_SYS_BUS_MB;
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if (aal)
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value |= DMA_SYS_BUS_AAL;
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writel(value, ioaddr + DMA_SYS_BUS_MODE);
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for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
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dwmac4_dma_init_channel(ioaddr, pbl, dma_tx, dma_rx, i);
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}
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static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel)
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{
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pr_debug(" Channel %d\n", channel);
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pr_debug("\tDMA_CHAN_CONTROL, offset: 0x%x, val: 0x%x\n", 0,
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readl(ioaddr + DMA_CHAN_CONTROL(channel)));
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pr_debug("\tDMA_CHAN_TX_CONTROL, offset: 0x%x, val: 0x%x\n", 0x4,
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readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)));
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pr_debug("\tDMA_CHAN_RX_CONTROL, offset: 0x%x, val: 0x%x\n", 0x8,
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readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)));
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pr_debug("\tDMA_CHAN_TX_BASE_ADDR, offset: 0x%x, val: 0x%x\n", 0x14,
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readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)));
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pr_debug("\tDMA_CHAN_RX_BASE_ADDR, offset: 0x%x, val: 0x%x\n", 0x1c,
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readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)));
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pr_debug("\tDMA_CHAN_TX_END_ADDR, offset: 0x%x, val: 0x%x\n", 0x20,
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readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel)));
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pr_debug("\tDMA_CHAN_RX_END_ADDR, offset: 0x%x, val: 0x%x\n", 0x28,
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readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel)));
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pr_debug("\tDMA_CHAN_TX_RING_LEN, offset: 0x%x, val: 0x%x\n", 0x2c,
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readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel)));
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pr_debug("\tDMA_CHAN_RX_RING_LEN, offset: 0x%x, val: 0x%x\n", 0x30,
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readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel)));
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pr_debug("\tDMA_CHAN_INTR_ENA, offset: 0x%x, val: 0x%x\n", 0x34,
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readl(ioaddr + DMA_CHAN_INTR_ENA(channel)));
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pr_debug("\tDMA_CHAN_RX_WATCHDOG, offset: 0x%x, val: 0x%x\n", 0x38,
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readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel)));
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pr_debug("\tDMA_CHAN_SLOT_CTRL_STATUS, offset: 0x%x, val: 0x%x\n", 0x3c,
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readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel)));
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pr_debug("\tDMA_CHAN_CUR_TX_DESC, offset: 0x%x, val: 0x%x\n", 0x44,
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readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel)));
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pr_debug("\tDMA_CHAN_CUR_RX_DESC, offset: 0x%x, val: 0x%x\n", 0x4c,
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readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel)));
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pr_debug("\tDMA_CHAN_CUR_TX_BUF_ADDR, offset: 0x%x, val: 0x%x\n", 0x54,
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readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel)));
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pr_debug("\tDMA_CHAN_CUR_RX_BUF_ADDR, offset: 0x%x, val: 0x%x\n", 0x5c,
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readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel)));
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pr_debug("\tDMA_CHAN_STATUS, offset: 0x%x, val: 0x%x\n", 0x60,
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readl(ioaddr + DMA_CHAN_STATUS(channel)));
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}
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static void dwmac4_dump_dma_regs(void __iomem *ioaddr)
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{
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int i;
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pr_debug(" GMAC4 DMA registers\n");
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for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
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_dwmac4_dump_dma_regs(ioaddr, i);
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}
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static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt)
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{
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int i;
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for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
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writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(i));
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}
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static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode,
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int rxmode, u32 channel)
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{
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u32 mtl_tx_op, mtl_rx_op, mtl_rx_int;
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/* Following code only done for channel 0, other channels not yet
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* supported.
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*/
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mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));
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if (txmode == SF_DMA_MODE) {
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pr_debug("GMAC: enable TX store and forward mode\n");
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/* Transmit COE type 2 cannot be done in cut-through mode. */
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mtl_tx_op |= MTL_OP_MODE_TSF;
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} else {
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pr_debug("GMAC: disabling TX SF (threshold %d)\n", txmode);
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mtl_tx_op &= ~MTL_OP_MODE_TSF;
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mtl_tx_op &= MTL_OP_MODE_TTC_MASK;
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/* Set the transmit threshold */
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if (txmode <= 32)
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mtl_tx_op |= MTL_OP_MODE_TTC_32;
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else if (txmode <= 64)
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mtl_tx_op |= MTL_OP_MODE_TTC_64;
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else if (txmode <= 96)
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mtl_tx_op |= MTL_OP_MODE_TTC_96;
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else if (txmode <= 128)
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mtl_tx_op |= MTL_OP_MODE_TTC_128;
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else if (txmode <= 192)
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mtl_tx_op |= MTL_OP_MODE_TTC_192;
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else if (txmode <= 256)
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mtl_tx_op |= MTL_OP_MODE_TTC_256;
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else if (txmode <= 384)
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mtl_tx_op |= MTL_OP_MODE_TTC_384;
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else
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mtl_tx_op |= MTL_OP_MODE_TTC_512;
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}
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writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel));
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mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));
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if (rxmode == SF_DMA_MODE) {
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pr_debug("GMAC: enable RX store and forward mode\n");
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mtl_rx_op |= MTL_OP_MODE_RSF;
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} else {
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pr_debug("GMAC: disable RX SF mode (threshold %d)\n", rxmode);
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mtl_rx_op &= ~MTL_OP_MODE_RSF;
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mtl_rx_op &= MTL_OP_MODE_RTC_MASK;
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if (rxmode <= 32)
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mtl_rx_op |= MTL_OP_MODE_RTC_32;
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else if (rxmode <= 64)
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mtl_rx_op |= MTL_OP_MODE_RTC_64;
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else if (rxmode <= 96)
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mtl_rx_op |= MTL_OP_MODE_RTC_96;
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else
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mtl_rx_op |= MTL_OP_MODE_RTC_128;
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}
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writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel));
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/* Enable MTL RX overflow */
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mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel));
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writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN,
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ioaddr + MTL_CHAN_INT_CTRL(channel));
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}
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static void dwmac4_dma_operation_mode(void __iomem *ioaddr, int txmode,
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int rxmode, int rxfifosz)
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{
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/* Only Channel 0 is actually configured and used */
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dwmac4_dma_chan_op_mode(ioaddr, txmode, rxmode, 0);
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}
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static void dwmac4_get_hw_feature(void __iomem *ioaddr,
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struct dma_features *dma_cap)
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{
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u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);
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/* MAC HW feature0 */
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dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL);
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dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1;
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dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2;
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dma_cap->hash_filter = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;
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dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18;
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dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3;
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dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5;
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dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6;
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dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7;
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/* MMC */
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dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8;
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/* IEEE 1588-2008 */
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dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12;
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/* 802.3az - Energy-Efficient Ethernet (EEE) */
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dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13;
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/* TX and RX csum */
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dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;
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dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;
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/* MAC HW feature1 */
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hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);
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dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;
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dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;
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/* MAC HW feature2 */
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hw_cap = readl(ioaddr + GMAC_HW_FEATURE2);
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/* TX and RX number of channels */
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dma_cap->number_rx_channel =
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((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1;
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dma_cap->number_tx_channel =
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((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1;
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/* IEEE 1588-2002 */
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dma_cap->time_stamp = 0;
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}
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/* Enable/disable TSO feature and set MSS */
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static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
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{
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u32 value;
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if (en) {
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/* enable TSO */
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value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
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writel(value | DMA_CONTROL_TSE,
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ioaddr + DMA_CHAN_TX_CONTROL(chan));
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} else {
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/* enable TSO */
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value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
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writel(value & ~DMA_CONTROL_TSE,
|
||
|
|
ioaddr + DMA_CHAN_TX_CONTROL(chan));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
const struct stmmac_dma_ops dwmac4_dma_ops = {
|
||
|
|
.reset = dwmac4_dma_reset,
|
||
|
|
.init = dwmac4_dma_init,
|
||
|
|
.axi = dwmac4_dma_axi,
|
||
|
|
.dump_regs = dwmac4_dump_dma_regs,
|
||
|
|
.dma_mode = dwmac4_dma_operation_mode,
|
||
|
|
.enable_dma_irq = dwmac4_enable_dma_irq,
|
||
|
|
.disable_dma_irq = dwmac4_disable_dma_irq,
|
||
|
|
.start_tx = dwmac4_dma_start_tx,
|
||
|
|
.stop_tx = dwmac4_dma_stop_tx,
|
||
|
|
.start_rx = dwmac4_dma_start_rx,
|
||
|
|
.stop_rx = dwmac4_dma_stop_rx,
|
||
|
|
.dma_interrupt = dwmac4_dma_interrupt,
|
||
|
|
.get_hw_feature = dwmac4_get_hw_feature,
|
||
|
|
.rx_watchdog = dwmac4_rx_watchdog,
|
||
|
|
.set_rx_ring_len = dwmac4_set_rx_ring_len,
|
||
|
|
.set_tx_ring_len = dwmac4_set_tx_ring_len,
|
||
|
|
.set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
|
||
|
|
.set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
|
||
|
|
.enable_tso = dwmac4_enable_tso,
|
||
|
|
};
|
||
|
|
|
||
|
|
const struct stmmac_dma_ops dwmac410_dma_ops = {
|
||
|
|
.reset = dwmac4_dma_reset,
|
||
|
|
.init = dwmac4_dma_init,
|
||
|
|
.axi = dwmac4_dma_axi,
|
||
|
|
.dump_regs = dwmac4_dump_dma_regs,
|
||
|
|
.dma_mode = dwmac4_dma_operation_mode,
|
||
|
|
.enable_dma_irq = dwmac410_enable_dma_irq,
|
||
|
|
.disable_dma_irq = dwmac4_disable_dma_irq,
|
||
|
|
.start_tx = dwmac4_dma_start_tx,
|
||
|
|
.stop_tx = dwmac4_dma_stop_tx,
|
||
|
|
.start_rx = dwmac4_dma_start_rx,
|
||
|
|
.stop_rx = dwmac4_dma_stop_rx,
|
||
|
|
.dma_interrupt = dwmac4_dma_interrupt,
|
||
|
|
.get_hw_feature = dwmac4_get_hw_feature,
|
||
|
|
.rx_watchdog = dwmac4_rx_watchdog,
|
||
|
|
.set_rx_ring_len = dwmac4_set_rx_ring_len,
|
||
|
|
.set_tx_ring_len = dwmac4_set_tx_ring_len,
|
||
|
|
.set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
|
||
|
|
.set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
|
||
|
|
.enable_tso = dwmac4_enable_tso,
|
||
|
|
};
|