345 lines
12 KiB
C
345 lines
12 KiB
C
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2012 Intel Corporation. All rights reserved.
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* Copyright (C) 2015 EMC Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* BSD LICENSE
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*
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* Copyright(c) 2012 Intel Corporation. All rights reserved.
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* Copyright (C) 2015 EMC Corporation. All Rights Reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copy
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Intel PCIe NTB Linux driver
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*
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* Contact Information:
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* Jon Mason <jon.mason@intel.com>
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*/
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#ifndef NTB_HW_INTEL_H
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#define NTB_HW_INTEL_H
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#include <linux/ntb.h>
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#include <linux/pci.h>
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF 0x3725
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#define PCI_DEVICE_ID_INTEL_NTB_PS_JSF 0x3726
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#define PCI_DEVICE_ID_INTEL_NTB_SS_JSF 0x3727
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_SNB 0x3C0D
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#define PCI_DEVICE_ID_INTEL_NTB_PS_SNB 0x3C0E
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#define PCI_DEVICE_ID_INTEL_NTB_SS_SNB 0x3C0F
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_IVT 0x0E0D
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#define PCI_DEVICE_ID_INTEL_NTB_PS_IVT 0x0E0E
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#define PCI_DEVICE_ID_INTEL_NTB_SS_IVT 0x0E0F
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_HSX 0x2F0D
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#define PCI_DEVICE_ID_INTEL_NTB_PS_HSX 0x2F0E
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#define PCI_DEVICE_ID_INTEL_NTB_SS_HSX 0x2F0F
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_BWD 0x0C4E
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_BDX 0x6F0D
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#define PCI_DEVICE_ID_INTEL_NTB_PS_BDX 0x6F0E
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#define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F
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/* Intel Xeon hardware */
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#define XEON_PBAR23LMT_OFFSET 0x0000
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#define XEON_PBAR45LMT_OFFSET 0x0008
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#define XEON_PBAR4LMT_OFFSET 0x0008
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#define XEON_PBAR5LMT_OFFSET 0x000c
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#define XEON_PBAR23XLAT_OFFSET 0x0010
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#define XEON_PBAR45XLAT_OFFSET 0x0018
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#define XEON_PBAR4XLAT_OFFSET 0x0018
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#define XEON_PBAR5XLAT_OFFSET 0x001c
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#define XEON_SBAR23LMT_OFFSET 0x0020
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#define XEON_SBAR45LMT_OFFSET 0x0028
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#define XEON_SBAR4LMT_OFFSET 0x0028
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#define XEON_SBAR5LMT_OFFSET 0x002c
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#define XEON_SBAR23XLAT_OFFSET 0x0030
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#define XEON_SBAR45XLAT_OFFSET 0x0038
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#define XEON_SBAR4XLAT_OFFSET 0x0038
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#define XEON_SBAR5XLAT_OFFSET 0x003c
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#define XEON_SBAR0BASE_OFFSET 0x0040
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#define XEON_SBAR23BASE_OFFSET 0x0048
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#define XEON_SBAR45BASE_OFFSET 0x0050
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#define XEON_SBAR4BASE_OFFSET 0x0050
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#define XEON_SBAR5BASE_OFFSET 0x0054
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#define XEON_SBDF_OFFSET 0x005c
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#define XEON_NTBCNTL_OFFSET 0x0058
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#define XEON_PDOORBELL_OFFSET 0x0060
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#define XEON_PDBMSK_OFFSET 0x0062
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#define XEON_SDOORBELL_OFFSET 0x0064
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#define XEON_SDBMSK_OFFSET 0x0066
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#define XEON_USMEMMISS_OFFSET 0x0070
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#define XEON_SPAD_OFFSET 0x0080
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#define XEON_PBAR23SZ_OFFSET 0x00d0
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#define XEON_PBAR45SZ_OFFSET 0x00d1
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#define XEON_PBAR4SZ_OFFSET 0x00d1
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#define XEON_SBAR23SZ_OFFSET 0x00d2
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#define XEON_SBAR45SZ_OFFSET 0x00d3
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#define XEON_SBAR4SZ_OFFSET 0x00d3
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#define XEON_PPD_OFFSET 0x00d4
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#define XEON_PBAR5SZ_OFFSET 0x00d5
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#define XEON_SBAR5SZ_OFFSET 0x00d6
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#define XEON_WCCNTRL_OFFSET 0x00e0
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#define XEON_UNCERRSTS_OFFSET 0x014c
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#define XEON_CORERRSTS_OFFSET 0x0158
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#define XEON_LINK_STATUS_OFFSET 0x01a2
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#define XEON_SPCICMD_OFFSET 0x0504
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#define XEON_DEVCTRL_OFFSET 0x0598
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#define XEON_DEVSTS_OFFSET 0x059a
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#define XEON_SLINK_STATUS_OFFSET 0x05a2
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#define XEON_B2B_SPAD_OFFSET 0x0100
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#define XEON_B2B_DOORBELL_OFFSET 0x0140
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#define XEON_B2B_XLAT_OFFSETL 0x0144
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#define XEON_B2B_XLAT_OFFSETU 0x0148
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#define XEON_PPD_CONN_MASK 0x03
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#define XEON_PPD_CONN_TRANSPARENT 0x00
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#define XEON_PPD_CONN_B2B 0x01
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#define XEON_PPD_CONN_RP 0x02
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#define XEON_PPD_DEV_MASK 0x10
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#define XEON_PPD_DEV_USD 0x00
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#define XEON_PPD_DEV_DSD 0x10
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#define XEON_PPD_SPLIT_BAR_MASK 0x40
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#define XEON_PPD_TOPO_MASK (XEON_PPD_CONN_MASK | XEON_PPD_DEV_MASK)
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#define XEON_PPD_TOPO_PRI_USD (XEON_PPD_CONN_RP | XEON_PPD_DEV_USD)
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#define XEON_PPD_TOPO_PRI_DSD (XEON_PPD_CONN_RP | XEON_PPD_DEV_DSD)
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#define XEON_PPD_TOPO_SEC_USD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_USD)
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#define XEON_PPD_TOPO_SEC_DSD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_DSD)
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#define XEON_PPD_TOPO_B2B_USD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_USD)
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#define XEON_PPD_TOPO_B2B_DSD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_DSD)
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#define XEON_MW_COUNT 2
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#define HSX_SPLIT_BAR_MW_COUNT 3
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#define XEON_DB_COUNT 15
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#define XEON_DB_LINK 15
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#define XEON_DB_LINK_BIT BIT_ULL(XEON_DB_LINK)
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#define XEON_DB_MSIX_VECTOR_COUNT 4
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#define XEON_DB_MSIX_VECTOR_SHIFT 5
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#define XEON_DB_TOTAL_SHIFT 16
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#define XEON_SPAD_COUNT 16
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/* Intel Atom hardware */
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#define ATOM_SBAR2XLAT_OFFSET 0x0008
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#define ATOM_PDOORBELL_OFFSET 0x0020
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#define ATOM_PDBMSK_OFFSET 0x0028
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#define ATOM_NTBCNTL_OFFSET 0x0060
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#define ATOM_SPAD_OFFSET 0x0080
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#define ATOM_PPD_OFFSET 0x00d4
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#define ATOM_PBAR2XLAT_OFFSET 0x8008
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#define ATOM_B2B_DOORBELL_OFFSET 0x8020
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#define ATOM_B2B_SPAD_OFFSET 0x8080
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#define ATOM_SPCICMD_OFFSET 0xb004
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#define ATOM_LINK_STATUS_OFFSET 0xb052
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#define ATOM_ERRCORSTS_OFFSET 0xb110
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#define ATOM_IP_BASE 0xc000
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#define ATOM_DESKEWSTS_OFFSET (ATOM_IP_BASE + 0x3024)
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#define ATOM_LTSSMERRSTS0_OFFSET (ATOM_IP_BASE + 0x3180)
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#define ATOM_LTSSMSTATEJMP_OFFSET (ATOM_IP_BASE + 0x3040)
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#define ATOM_IBSTERRRCRVSTS0_OFFSET (ATOM_IP_BASE + 0x3324)
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#define ATOM_MODPHY_PCSREG4 0x1c004
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#define ATOM_MODPHY_PCSREG6 0x1c006
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#define ATOM_PPD_INIT_LINK 0x0008
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#define ATOM_PPD_CONN_MASK 0x0300
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#define ATOM_PPD_CONN_TRANSPARENT 0x0000
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#define ATOM_PPD_CONN_B2B 0x0100
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#define ATOM_PPD_CONN_RP 0x0200
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#define ATOM_PPD_DEV_MASK 0x1000
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#define ATOM_PPD_DEV_USD 0x0000
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#define ATOM_PPD_DEV_DSD 0x1000
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#define ATOM_PPD_TOPO_MASK (ATOM_PPD_CONN_MASK | ATOM_PPD_DEV_MASK)
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#define ATOM_PPD_TOPO_PRI_USD (ATOM_PPD_CONN_TRANSPARENT | ATOM_PPD_DEV_USD)
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#define ATOM_PPD_TOPO_PRI_DSD (ATOM_PPD_CONN_TRANSPARENT | ATOM_PPD_DEV_DSD)
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#define ATOM_PPD_TOPO_SEC_USD (ATOM_PPD_CONN_RP | ATOM_PPD_DEV_USD)
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#define ATOM_PPD_TOPO_SEC_DSD (ATOM_PPD_CONN_RP | ATOM_PPD_DEV_DSD)
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#define ATOM_PPD_TOPO_B2B_USD (ATOM_PPD_CONN_B2B | ATOM_PPD_DEV_USD)
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#define ATOM_PPD_TOPO_B2B_DSD (ATOM_PPD_CONN_B2B | ATOM_PPD_DEV_DSD)
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#define ATOM_MW_COUNT 2
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#define ATOM_DB_COUNT 34
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#define ATOM_DB_VALID_MASK (BIT_ULL(ATOM_DB_COUNT) - 1)
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#define ATOM_DB_MSIX_VECTOR_COUNT 34
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#define ATOM_DB_MSIX_VECTOR_SHIFT 1
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#define ATOM_DB_TOTAL_SHIFT 34
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#define ATOM_SPAD_COUNT 16
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#define ATOM_NTB_CTL_DOWN_BIT BIT(16)
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#define ATOM_NTB_CTL_ACTIVE(x) !(x & ATOM_NTB_CTL_DOWN_BIT)
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#define ATOM_DESKEWSTS_DBERR BIT(15)
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#define ATOM_LTSSMERRSTS0_UNEXPECTEDEI BIT(20)
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#define ATOM_LTSSMSTATEJMP_FORCEDETECT BIT(2)
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#define ATOM_IBIST_ERR_OFLOW 0x7FFF7FFF
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#define ATOM_LINK_HB_TIMEOUT msecs_to_jiffies(1000)
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#define ATOM_LINK_RECOVERY_TIME msecs_to_jiffies(500)
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/* Ntb control and link status */
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#define NTB_CTL_CFG_LOCK BIT(0)
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#define NTB_CTL_DISABLE BIT(1)
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#define NTB_CTL_S2P_BAR2_SNOOP BIT(2)
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#define NTB_CTL_P2S_BAR2_SNOOP BIT(4)
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#define NTB_CTL_S2P_BAR4_SNOOP BIT(6)
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#define NTB_CTL_P2S_BAR4_SNOOP BIT(8)
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#define NTB_CTL_S2P_BAR5_SNOOP BIT(12)
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#define NTB_CTL_P2S_BAR5_SNOOP BIT(14)
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#define NTB_LNK_STA_ACTIVE_BIT 0x2000
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#define NTB_LNK_STA_SPEED_MASK 0x000f
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#define NTB_LNK_STA_WIDTH_MASK 0x03f0
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#define NTB_LNK_STA_ACTIVE(x) (!!((x) & NTB_LNK_STA_ACTIVE_BIT))
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#define NTB_LNK_STA_SPEED(x) ((x) & NTB_LNK_STA_SPEED_MASK)
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#define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 4)
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/* Use the following addresses for translation between b2b ntb devices in case
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* the hardware default values are not reliable. */
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#define XEON_B2B_BAR0_ADDR 0x1000000000000000ull
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#define XEON_B2B_BAR2_ADDR64 0x2000000000000000ull
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#define XEON_B2B_BAR4_ADDR64 0x4000000000000000ull
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#define XEON_B2B_BAR4_ADDR32 0x20000000u
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#define XEON_B2B_BAR5_ADDR32 0x40000000u
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/* The peer ntb secondary config space is 32KB fixed size */
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#define XEON_B2B_MIN_SIZE 0x8000
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/* flags to indicate hardware errata */
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#define NTB_HWERR_SDOORBELL_LOCKUP BIT_ULL(0)
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#define NTB_HWERR_SB01BASE_LOCKUP BIT_ULL(1)
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#define NTB_HWERR_B2BDOORBELL_BIT14 BIT_ULL(2)
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/* flags to indicate unsafe api */
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#define NTB_UNSAFE_DB BIT_ULL(0)
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#define NTB_UNSAFE_SPAD BIT_ULL(1)
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#define NTB_BAR_MASK_64 ~(0xfull)
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#define NTB_BAR_MASK_32 ~(0xfu)
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struct intel_ntb_dev;
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struct intel_ntb_reg {
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int (*poll_link)(struct intel_ntb_dev *ndev);
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int (*link_is_up)(struct intel_ntb_dev *ndev);
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u64 (*db_ioread)(void __iomem *mmio);
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void (*db_iowrite)(u64 db_bits, void __iomem *mmio);
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unsigned long ntb_ctl;
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resource_size_t db_size;
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int mw_bar[];
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};
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struct intel_ntb_alt_reg {
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unsigned long db_bell;
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unsigned long db_mask;
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unsigned long spad;
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};
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struct intel_ntb_xlat_reg {
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unsigned long bar0_base;
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unsigned long bar2_xlat;
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unsigned long bar2_limit;
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};
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struct intel_b2b_addr {
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phys_addr_t bar0_addr;
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phys_addr_t bar2_addr64;
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phys_addr_t bar4_addr64;
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phys_addr_t bar4_addr32;
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phys_addr_t bar5_addr32;
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};
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struct intel_ntb_vec {
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struct intel_ntb_dev *ndev;
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int num;
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};
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struct intel_ntb_dev {
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struct ntb_dev ntb;
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/* offset of peer bar0 in b2b bar */
|
||
|
|
unsigned long b2b_off;
|
||
|
|
/* mw idx used to access peer bar0 */
|
||
|
|
unsigned int b2b_idx;
|
||
|
|
|
||
|
|
/* BAR45 is split into BAR4 and BAR5 */
|
||
|
|
bool bar4_split;
|
||
|
|
|
||
|
|
u32 ntb_ctl;
|
||
|
|
u32 lnk_sta;
|
||
|
|
|
||
|
|
unsigned char mw_count;
|
||
|
|
unsigned char spad_count;
|
||
|
|
unsigned char db_count;
|
||
|
|
unsigned char db_vec_count;
|
||
|
|
unsigned char db_vec_shift;
|
||
|
|
|
||
|
|
u64 db_valid_mask;
|
||
|
|
u64 db_link_mask;
|
||
|
|
u64 db_mask;
|
||
|
|
|
||
|
|
/* synchronize rmw access of db_mask and hw reg */
|
||
|
|
spinlock_t db_mask_lock;
|
||
|
|
|
||
|
|
struct msix_entry *msix;
|
||
|
|
struct intel_ntb_vec *vec;
|
||
|
|
|
||
|
|
const struct intel_ntb_reg *reg;
|
||
|
|
const struct intel_ntb_alt_reg *self_reg;
|
||
|
|
const struct intel_ntb_alt_reg *peer_reg;
|
||
|
|
const struct intel_ntb_xlat_reg *xlat_reg;
|
||
|
|
void __iomem *self_mmio;
|
||
|
|
void __iomem *peer_mmio;
|
||
|
|
phys_addr_t peer_addr;
|
||
|
|
|
||
|
|
unsigned long last_ts;
|
||
|
|
struct delayed_work hb_timer;
|
||
|
|
|
||
|
|
unsigned long hwerr_flags;
|
||
|
|
unsigned long unsafe_flags;
|
||
|
|
unsigned long unsafe_flags_ignore;
|
||
|
|
|
||
|
|
struct dentry *debugfs_dir;
|
||
|
|
struct dentry *debugfs_info;
|
||
|
|
};
|
||
|
|
|
||
|
|
#define ndev_pdev(ndev) ((ndev)->ntb.pdev)
|
||
|
|
#define ndev_name(ndev) pci_name(ndev_pdev(ndev))
|
||
|
|
#define ndev_dev(ndev) (&ndev_pdev(ndev)->dev)
|
||
|
|
#define ntb_ndev(__ntb) container_of(__ntb, struct intel_ntb_dev, ntb)
|
||
|
|
#define hb_ndev(__work) container_of(__work, struct intel_ntb_dev, \
|
||
|
|
hb_timer.work)
|
||
|
|
|
||
|
|
#endif
|