449 lines
11 KiB
C
449 lines
11 KiB
C
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/**
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* Synopsys DesignWare PCIe Endpoint controller driver
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*
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* Copyright (C) 2017 Texas Instruments
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* Author: Kishon Vijay Abraham I <kishon@ti.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 of
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* the License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/of.h>
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#include "pcie-designware.h"
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#include <linux/pci-epc.h>
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#include <linux/pci-epf.h>
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void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
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{
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struct pci_epc *epc = ep->epc;
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pci_epc_linkup(epc);
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}
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static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
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{
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u32 reg;
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reg = PCI_BASE_ADDRESS_0 + (4 * bar);
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dw_pcie_writel_dbi2(pci, reg, 0x0);
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dw_pcie_writel_dbi(pci, reg, 0x0);
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}
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static void dw_pcie_ep_write_header_regs(struct dw_pcie_ep *ep)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct pci_epf_header *hdr = &(ep->cached_hdr);
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dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid);
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dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid);
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dw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid);
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dw_pcie_writeb_dbi(pci, PCI_CLASS_PROG, hdr->progif_code);
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dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE,
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hdr->subclass_code | hdr->baseclass_code << 8);
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dw_pcie_writeb_dbi(pci, PCI_CACHE_LINE_SIZE,
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hdr->cache_line_size);
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dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_VENDOR_ID,
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hdr->subsys_vendor_id);
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dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id);
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dw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN,
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hdr->interrupt_pin);
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return;
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}
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static int dw_pcie_ep_write_header(struct pci_epc *epc,
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struct pci_epf_header *hdr)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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ep->cached_hdr = *hdr;
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if (ep->hw_regs_not_available)
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return 0;
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dw_pcie_ep_write_header_regs(ep);
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return 0;
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}
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static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
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dma_addr_t cpu_addr,
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enum dw_pcie_as_type as_type)
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{
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int ret;
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u32 free_win;
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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free_win = find_first_zero_bit(&ep->ib_window_map,
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sizeof(ep->ib_window_map));
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if (free_win >= ep->num_ib_windows) {
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dev_err(pci->dev, "no free inbound window\n");
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return -EINVAL;
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}
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ep->cached_inbound_atus[free_win].bar = bar;
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ep->cached_inbound_atus[free_win].cpu_addr = cpu_addr;
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ep->cached_inbound_atus[free_win].as_type = as_type;
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ep->cached_bars[bar].atu_index = free_win;
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set_bit(free_win, &ep->ib_window_map);
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if (ep->hw_regs_not_available)
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return 0;
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ret = dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr,
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as_type);
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if (ret < 0) {
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dev_err(pci->dev, "Failed to program IB window\n");
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return ret;
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}
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return 0;
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}
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static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr,
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u64 pci_addr, size_t size)
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{
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u32 free_win;
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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free_win = find_first_zero_bit(&ep->ob_window_map,
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sizeof(ep->ob_window_map));
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if (free_win >= ep->num_ob_windows) {
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dev_err(pci->dev, "no free outbound window\n");
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return -EINVAL;
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}
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ep->cached_outbound_atus[free_win].addr = phys_addr;
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ep->cached_outbound_atus[free_win].pci_addr = pci_addr;
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ep->cached_outbound_atus[free_win].size = size;
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set_bit(free_win, &ep->ob_window_map);
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if (ep->hw_regs_not_available)
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return 0;
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dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
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phys_addr, pci_addr, size);
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return 0;
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}
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static void dw_pcie_ep_clear_bar_regs(struct dw_pcie_ep *ep,
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enum pci_barno bar)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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u32 atu_index = ep->cached_bars[bar].atu_index;
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dw_pcie_ep_reset_bar(pci, bar);
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dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
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}
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static void dw_pcie_ep_clear_bar(struct pci_epc *epc, enum pci_barno bar)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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u32 atu_index = ep->cached_bars[bar].atu_index;
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clear_bit(atu_index, &ep->ib_window_map);
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if (ep->hw_regs_not_available)
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return;
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dw_pcie_ep_clear_bar_regs(ep, bar);
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}
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static void dw_pcie_ep_set_bar_regs(struct dw_pcie_ep *ep, enum pci_barno bar)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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size_t size = ep->cached_bars[bar].size;
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int flags = ep->cached_bars[bar].flags;
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u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
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dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));
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dw_pcie_writel_dbi(pci, reg, flags);
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if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
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dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));
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dw_pcie_writel_dbi(pci, reg + 4, 0);
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}
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}
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static int dw_pcie_ep_set_bar(struct pci_epc *epc, enum pci_barno bar,
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dma_addr_t bar_phys, size_t size, int flags)
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{
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int ret;
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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enum dw_pcie_as_type as_type;
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if (!(flags & PCI_BASE_ADDRESS_SPACE))
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as_type = DW_PCIE_AS_MEM;
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else
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as_type = DW_PCIE_AS_IO;
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ret = dw_pcie_ep_inbound_atu(ep, bar, bar_phys, as_type);
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if (ret)
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return ret;
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ep->cached_bars[bar].size = size;
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ep->cached_bars[bar].flags = flags;
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if (ep->hw_regs_not_available)
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return 0;
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dw_pcie_ep_set_bar_regs(ep, bar);
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return 0;
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}
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static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr,
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u32 *atu_index)
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{
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u32 index;
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for (index = 0; index < ep->num_ob_windows; index++) {
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if (ep->cached_outbound_atus[index].addr != addr)
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continue;
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*atu_index = index;
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return 0;
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}
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return -EINVAL;
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}
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static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, phys_addr_t addr)
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{
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int ret;
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u32 atu_index;
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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ret = dw_pcie_find_index(ep, addr, &atu_index);
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if (ret < 0)
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return;
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clear_bit(atu_index, &ep->ob_window_map);
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if (ep->hw_regs_not_available)
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return;
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dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND);
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}
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static int dw_pcie_ep_map_addr(struct pci_epc *epc, phys_addr_t addr,
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u64 pci_addr, size_t size)
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{
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int ret;
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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ret = dw_pcie_ep_outbound_atu(ep, addr, pci_addr, size);
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if (ret) {
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dev_err(pci->dev, "failed to enable address\n");
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return ret;
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}
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return 0;
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}
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static int dw_pcie_ep_get_msi(struct pci_epc *epc)
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{
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int val;
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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if (ep->hw_regs_not_available)
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val = ep->cached_msi_ctrl;
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else
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val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
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if (!(val & MSI_CAP_MSI_EN_MASK))
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return -EINVAL;
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val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
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return val;
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}
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static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int)
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{
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int val;
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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val = (encode_int << MSI_CAP_MMC_SHIFT);
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ep->cached_msi_ctrl = val;
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if (ep->hw_regs_not_available)
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return 0;
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dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
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return 0;
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}
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void dw_pcie_set_regs_available(struct dw_pcie *pci)
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{
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struct dw_pcie_ep *ep = &(pci->ep);
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int i;
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ep->hw_regs_not_available = false;
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dw_pcie_ep_write_header_regs(ep);
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for_each_set_bit(i, &ep->ib_window_map, ep->num_ib_windows) {
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dw_pcie_prog_inbound_atu(pci, i,
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ep->cached_inbound_atus[i].bar,
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ep->cached_inbound_atus[i].cpu_addr,
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ep->cached_inbound_atus[i].as_type);
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dw_pcie_ep_set_bar_regs(ep, ep->cached_inbound_atus[i].bar);
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}
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for_each_set_bit(i, &ep->ob_window_map, ep->num_ob_windows)
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dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM,
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ep->cached_outbound_atus[i].addr,
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ep->cached_outbound_atus[i].pci_addr,
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ep->cached_outbound_atus[i].size);
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dw_pcie_dbi_ro_wr_en(pci);
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dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, ep->cached_msi_ctrl);
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dw_pcie_dbi_ro_wr_dis(pci);
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}
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static int dw_pcie_ep_raise_irq(struct pci_epc *epc,
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enum pci_epc_irq_type type, u8 interrupt_num)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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if (!ep->ops->raise_irq)
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return -EINVAL;
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if (ep->hw_regs_not_available)
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return -EAGAIN;
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return ep->ops->raise_irq(ep, type, interrupt_num);
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}
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static void dw_pcie_ep_stop(struct pci_epc *epc)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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if (!pci->ops->stop_link)
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return;
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pci->ops->stop_link(pci);
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}
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static int dw_pcie_ep_start(struct pci_epc *epc)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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if (!pci->ops->start_link)
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return -EINVAL;
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return pci->ops->start_link(pci);
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}
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static const struct pci_epc_ops epc_ops = {
|
||
|
|
.write_header = dw_pcie_ep_write_header,
|
||
|
|
.set_bar = dw_pcie_ep_set_bar,
|
||
|
|
.clear_bar = dw_pcie_ep_clear_bar,
|
||
|
|
.map_addr = dw_pcie_ep_map_addr,
|
||
|
|
.unmap_addr = dw_pcie_ep_unmap_addr,
|
||
|
|
.set_msi = dw_pcie_ep_set_msi,
|
||
|
|
.get_msi = dw_pcie_ep_get_msi,
|
||
|
|
.raise_irq = dw_pcie_ep_raise_irq,
|
||
|
|
.start = dw_pcie_ep_start,
|
||
|
|
.stop = dw_pcie_ep_stop,
|
||
|
|
};
|
||
|
|
|
||
|
|
void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
|
||
|
|
{
|
||
|
|
struct pci_epc *epc = ep->epc;
|
||
|
|
|
||
|
|
pci_epc_mem_exit(epc);
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL(dw_pcie_ep_exit);
|
||
|
|
|
||
|
|
int dw_pcie_ep_init(struct dw_pcie_ep *ep)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
struct pci_epc *epc;
|
||
|
|
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
||
|
|
struct device *dev = pci->dev;
|
||
|
|
struct device_node *np = dev->of_node;
|
||
|
|
|
||
|
|
if (!pci->dbi_base || !pci->dbi_base2) {
|
||
|
|
dev_err(dev, "dbi_base/deb_base2 is not populated\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
if (pci->iatu_unroll_enabled && !pci->atu_base) {
|
||
|
|
dev_err(dev, "atu_base is not populated\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows);
|
||
|
|
if (ret < 0) {
|
||
|
|
dev_err(dev, "unable to read *num-ib-windows* property\n");
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
ep->cached_inbound_atus = devm_kzalloc(dev,
|
||
|
|
sizeof(ep->cached_inbound_atus[0]) * ep->num_ib_windows,
|
||
|
|
GFP_KERNEL);
|
||
|
|
if (!ep->cached_inbound_atus)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
|
||
|
|
if (ret < 0) {
|
||
|
|
dev_err(dev, "unable to read *num-ob-windows* property\n");
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
ep->cached_outbound_atus = devm_kzalloc(dev,
|
||
|
|
sizeof(ep->cached_outbound_atus[0]) * ep->num_ob_windows,
|
||
|
|
GFP_KERNEL);
|
||
|
|
if (!ep->cached_outbound_atus)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
if (ep->ops->ep_init)
|
||
|
|
ep->ops->ep_init(ep);
|
||
|
|
|
||
|
|
epc = devm_pci_epc_create(dev, &epc_ops);
|
||
|
|
if (IS_ERR(epc)) {
|
||
|
|
dev_err(dev, "failed to create epc device\n");
|
||
|
|
return PTR_ERR(epc);
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
|
||
|
|
if (ret < 0)
|
||
|
|
epc->max_functions = 1;
|
||
|
|
|
||
|
|
ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
|
||
|
|
ep->page_size);
|
||
|
|
if (ret < 0) {
|
||
|
|
dev_err(dev, "Failed to initialize address space\n");
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
|
||
|
|
epc->mem->page_size);
|
||
|
|
if (!ep->msi_mem) {
|
||
|
|
dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
|
||
|
|
return -ENOMEM;
|
||
|
|
}
|
||
|
|
|
||
|
|
ep->epc = epc;
|
||
|
|
epc_set_drvdata(epc, ep);
|
||
|
|
if (ep->ops->ep_setup)
|
||
|
|
ep->ops->ep_setup(ep);
|
||
|
|
else
|
||
|
|
dw_pcie_setup(pci);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL(dw_pcie_ep_init);
|