526 lines
12 KiB
C
526 lines
12 KiB
C
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/*
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* pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
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*
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* Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
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*
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* Authors: Kishon Vijay Abraham I <kishon@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of_gpio.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/resource.h>
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#include <linux/types.h>
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#include "pcie-designware.h"
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/* PCIe controller wrapper DRA7XX configuration registers */
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#define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024
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#define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028
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#define ERR_SYS BIT(0)
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#define ERR_FATAL BIT(1)
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#define ERR_NONFATAL BIT(2)
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#define ERR_COR BIT(3)
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#define ERR_AXI BIT(4)
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#define ERR_ECRC BIT(5)
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#define PME_TURN_OFF BIT(8)
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#define PME_TO_ACK BIT(9)
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#define PM_PME BIT(10)
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#define LINK_REQ_RST BIT(11)
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#define LINK_UP_EVT BIT(12)
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#define CFG_BME_EVT BIT(13)
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#define CFG_MSE_EVT BIT(14)
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#define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
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ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
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LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)
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#define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034
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#define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038
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#define INTA BIT(0)
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#define INTB BIT(1)
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#define INTC BIT(2)
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#define INTD BIT(3)
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#define MSI BIT(4)
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#define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
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#define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
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#define LTSSM_EN 0x1
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#define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
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#define LINK_UP BIT(16)
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#define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF
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struct dra7xx_pcie {
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struct pcie_port pp;
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void __iomem *base; /* DT ti_conf */
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int phy_count; /* DT phy-names count */
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struct phy **phy;
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};
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#define to_dra7xx_pcie(x) container_of((x), struct dra7xx_pcie, pp)
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static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
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{
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return readl(pcie->base + offset);
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}
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static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
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u32 value)
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{
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writel(value, pcie->base + offset);
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}
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static int dra7xx_pcie_link_up(struct pcie_port *pp)
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{
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
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u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
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return !!(reg & LINK_UP);
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}
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static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
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{
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struct pcie_port *pp = &dra7xx->pp;
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struct device *dev = pp->dev;
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u32 reg;
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if (dw_pcie_link_up(pp)) {
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dev_err(dev, "link is already up\n");
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return 0;
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}
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reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
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reg |= LTSSM_EN;
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
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return dw_pcie_wait_for_link(pp);
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}
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static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
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{
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
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~INTERRUPTS);
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dra7xx_pcie_writel(dra7xx,
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PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, INTERRUPTS);
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
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~LEG_EP_INTERRUPTS & ~MSI);
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if (IS_ENABLED(CONFIG_PCI_MSI))
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dra7xx_pcie_writel(dra7xx,
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PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, MSI);
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else
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dra7xx_pcie_writel(dra7xx,
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PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
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LEG_EP_INTERRUPTS);
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}
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static void dra7xx_pcie_host_init(struct pcie_port *pp)
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{
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
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pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
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pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
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pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
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pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR;
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dw_pcie_setup_rc(pp);
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dra7xx_pcie_establish_link(dra7xx);
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if (IS_ENABLED(CONFIG_PCI_MSI))
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dw_pcie_msi_init(pp);
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dra7xx_pcie_enable_interrupts(dra7xx);
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}
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static struct pcie_host_ops dra7xx_pcie_host_ops = {
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.link_up = dra7xx_pcie_link_up,
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.host_init = dra7xx_pcie_host_init,
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};
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static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
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irq_set_chip_data(irq, domain->host_data);
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return 0;
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}
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static const struct irq_domain_ops intx_domain_ops = {
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.map = dra7xx_pcie_intx_map,
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};
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static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
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{
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struct device *dev = pp->dev;
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struct device_node *node = dev->of_node;
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struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
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if (!pcie_intc_node) {
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dev_err(dev, "No PCIe Intc node found\n");
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return -ENODEV;
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}
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pp->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
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&intx_domain_ops, pp);
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if (!pp->irq_domain) {
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dev_err(dev, "Failed to get a INTx IRQ domain\n");
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return -ENODEV;
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}
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return 0;
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}
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static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
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{
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struct dra7xx_pcie *dra7xx = arg;
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struct pcie_port *pp = &dra7xx->pp;
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u32 reg;
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reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
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switch (reg) {
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case MSI:
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dw_handle_msi_irq(pp);
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break;
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case INTA:
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case INTB:
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case INTC:
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case INTD:
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generic_handle_irq(irq_find_mapping(pp->irq_domain, ffs(reg)));
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break;
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}
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
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return IRQ_HANDLED;
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}
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static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
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{
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struct dra7xx_pcie *dra7xx = arg;
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struct device *dev = dra7xx->pp.dev;
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u32 reg;
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reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
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if (reg & ERR_SYS)
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dev_dbg(dev, "System Error\n");
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if (reg & ERR_FATAL)
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dev_dbg(dev, "Fatal Error\n");
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if (reg & ERR_NONFATAL)
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dev_dbg(dev, "Non Fatal Error\n");
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if (reg & ERR_COR)
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dev_dbg(dev, "Correctable Error\n");
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if (reg & ERR_AXI)
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dev_dbg(dev, "AXI tag lookup fatal Error\n");
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if (reg & ERR_ECRC)
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dev_dbg(dev, "ECRC Error\n");
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if (reg & PME_TURN_OFF)
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dev_dbg(dev,
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"Power Management Event Turn-Off message received\n");
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if (reg & PME_TO_ACK)
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dev_dbg(dev,
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"Power Management Turn-Off Ack message received\n");
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if (reg & PM_PME)
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dev_dbg(dev, "PM Power Management Event message received\n");
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if (reg & LINK_REQ_RST)
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dev_dbg(dev, "Link Request Reset\n");
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if (reg & LINK_UP_EVT)
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dev_dbg(dev, "Link-up state change\n");
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if (reg & CFG_BME_EVT)
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dev_dbg(dev, "CFG 'Bus Master Enable' change\n");
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if (reg & CFG_MSE_EVT)
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dev_dbg(dev, "CFG 'Memory Space Enable' change\n");
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
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return IRQ_HANDLED;
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}
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static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
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struct platform_device *pdev)
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{
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int ret;
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struct pcie_port *pp = &dra7xx->pp;
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struct device *dev = pp->dev;
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struct resource *res;
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pp->irq = platform_get_irq(pdev, 1);
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if (pp->irq < 0) {
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dev_err(dev, "missing IRQ resource\n");
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return -EINVAL;
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}
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ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler,
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IRQF_SHARED | IRQF_NO_THREAD,
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"dra7-pcie-msi", dra7xx);
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if (ret) {
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dev_err(dev, "failed to request irq\n");
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return ret;
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}
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if (!IS_ENABLED(CONFIG_PCI_MSI)) {
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ret = dra7xx_pcie_init_irq_domain(pp);
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if (ret < 0)
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return ret;
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
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pp->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
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if (!pp->dbi_base)
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return -ENOMEM;
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ret = dw_pcie_host_init(pp);
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if (ret) {
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dev_err(dev, "failed to initialize host\n");
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return ret;
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}
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return 0;
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}
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static int __init dra7xx_pcie_probe(struct platform_device *pdev)
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{
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u32 reg;
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int ret;
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int irq;
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int i;
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int phy_count;
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struct phy **phy;
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void __iomem *base;
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struct resource *res;
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struct dra7xx_pcie *dra7xx;
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struct pcie_port *pp;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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char name[10];
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int gpio_sel;
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enum of_gpio_flags flags;
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unsigned long gpio_flags;
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dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
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if (!dra7xx)
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return -ENOMEM;
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pp = &dra7xx->pp;
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pp->dev = dev;
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pp->ops = &dra7xx_pcie_host_ops;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(dev, "missing IRQ resource\n");
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return -EINVAL;
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}
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ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
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IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
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if (ret) {
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dev_err(dev, "failed to request irq\n");
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return ret;
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
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base = devm_ioremap_nocache(dev, res->start, resource_size(res));
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if (!base)
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return -ENOMEM;
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phy_count = of_property_count_strings(np, "phy-names");
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if (phy_count < 0) {
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dev_err(dev, "unable to find the strings\n");
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return phy_count;
|
||
|
|
}
|
||
|
|
|
||
|
|
phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
|
||
|
|
if (!phy)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
for (i = 0; i < phy_count; i++) {
|
||
|
|
snprintf(name, sizeof(name), "pcie-phy%d", i);
|
||
|
|
phy[i] = devm_phy_get(dev, name);
|
||
|
|
if (IS_ERR(phy[i]))
|
||
|
|
return PTR_ERR(phy[i]);
|
||
|
|
|
||
|
|
ret = phy_init(phy[i]);
|
||
|
|
if (ret < 0)
|
||
|
|
goto err_phy;
|
||
|
|
|
||
|
|
ret = phy_power_on(phy[i]);
|
||
|
|
if (ret < 0) {
|
||
|
|
phy_exit(phy[i]);
|
||
|
|
goto err_phy;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
dra7xx->base = base;
|
||
|
|
dra7xx->phy = phy;
|
||
|
|
dra7xx->phy_count = phy_count;
|
||
|
|
|
||
|
|
pm_runtime_enable(dev);
|
||
|
|
ret = pm_runtime_get_sync(dev);
|
||
|
|
if (ret < 0) {
|
||
|
|
dev_err(dev, "pm_runtime_get_sync failed\n");
|
||
|
|
goto err_get_sync;
|
||
|
|
}
|
||
|
|
|
||
|
|
gpio_sel = of_get_gpio_flags(dev->of_node, 0, &flags);
|
||
|
|
if (gpio_is_valid(gpio_sel)) {
|
||
|
|
gpio_flags = (flags & OF_GPIO_ACTIVE_LOW) ?
|
||
|
|
GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH;
|
||
|
|
ret = devm_gpio_request_one(dev, gpio_sel, gpio_flags,
|
||
|
|
"pcie_reset");
|
||
|
|
if (ret) {
|
||
|
|
dev_err(dev, "gpio%d request failed, ret %d\n",
|
||
|
|
gpio_sel, ret);
|
||
|
|
goto err_gpio;
|
||
|
|
}
|
||
|
|
} else if (gpio_sel == -EPROBE_DEFER) {
|
||
|
|
ret = -EPROBE_DEFER;
|
||
|
|
goto err_gpio;
|
||
|
|
}
|
||
|
|
|
||
|
|
reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
|
||
|
|
reg &= ~LTSSM_EN;
|
||
|
|
dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
|
||
|
|
|
||
|
|
ret = dra7xx_add_pcie_port(dra7xx, pdev);
|
||
|
|
if (ret < 0)
|
||
|
|
goto err_gpio;
|
||
|
|
|
||
|
|
platform_set_drvdata(pdev, dra7xx);
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
err_gpio:
|
||
|
|
pm_runtime_put(dev);
|
||
|
|
|
||
|
|
err_get_sync:
|
||
|
|
pm_runtime_disable(dev);
|
||
|
|
|
||
|
|
err_phy:
|
||
|
|
while (--i >= 0) {
|
||
|
|
phy_power_off(phy[i]);
|
||
|
|
phy_exit(phy[i]);
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_PM_SLEEP
|
||
|
|
static int dra7xx_pcie_suspend(struct device *dev)
|
||
|
|
{
|
||
|
|
struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
|
||
|
|
struct pcie_port *pp = &dra7xx->pp;
|
||
|
|
u32 val;
|
||
|
|
|
||
|
|
/* clear MSE */
|
||
|
|
val = dw_pcie_readl_rc(pp, PCI_COMMAND);
|
||
|
|
val &= ~PCI_COMMAND_MEMORY;
|
||
|
|
dw_pcie_writel_rc(pp, PCI_COMMAND, val);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int dra7xx_pcie_resume(struct device *dev)
|
||
|
|
{
|
||
|
|
struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
|
||
|
|
struct pcie_port *pp = &dra7xx->pp;
|
||
|
|
u32 val;
|
||
|
|
|
||
|
|
/* set MSE */
|
||
|
|
val = dw_pcie_readl_rc(pp, PCI_COMMAND);
|
||
|
|
val |= PCI_COMMAND_MEMORY;
|
||
|
|
dw_pcie_writel_rc(pp, PCI_COMMAND, val);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int dra7xx_pcie_suspend_noirq(struct device *dev)
|
||
|
|
{
|
||
|
|
struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
|
||
|
|
int count = dra7xx->phy_count;
|
||
|
|
|
||
|
|
while (count--) {
|
||
|
|
phy_power_off(dra7xx->phy[count]);
|
||
|
|
phy_exit(dra7xx->phy[count]);
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int dra7xx_pcie_resume_noirq(struct device *dev)
|
||
|
|
{
|
||
|
|
struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
|
||
|
|
int phy_count = dra7xx->phy_count;
|
||
|
|
int ret;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
for (i = 0; i < phy_count; i++) {
|
||
|
|
ret = phy_init(dra7xx->phy[i]);
|
||
|
|
if (ret < 0)
|
||
|
|
goto err_phy;
|
||
|
|
|
||
|
|
ret = phy_power_on(dra7xx->phy[i]);
|
||
|
|
if (ret < 0) {
|
||
|
|
phy_exit(dra7xx->phy[i]);
|
||
|
|
goto err_phy;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
err_phy:
|
||
|
|
while (--i >= 0) {
|
||
|
|
phy_power_off(dra7xx->phy[i]);
|
||
|
|
phy_exit(dra7xx->phy[i]);
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
|
||
|
|
SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
|
||
|
|
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
|
||
|
|
dra7xx_pcie_resume_noirq)
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id of_dra7xx_pcie_match[] = {
|
||
|
|
{ .compatible = "ti,dra7-pcie", },
|
||
|
|
{},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_driver dra7xx_pcie_driver = {
|
||
|
|
.driver = {
|
||
|
|
.name = "dra7-pcie",
|
||
|
|
.of_match_table = of_dra7xx_pcie_match,
|
||
|
|
.suppress_bind_attrs = true,
|
||
|
|
.pm = &dra7xx_pcie_pm_ops,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);
|