255 lines
6.9 KiB
C
255 lines
6.9 KiB
C
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/*
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* PCIe host controller driver for Marvell Armada-8K SoCs
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*
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* Armada-8K PCIe Glue Layer Source Code
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*
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* Copyright (C) 2016 Marvell Technology Group Ltd.
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*
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* Author: Yehuda Yitshak <yehuday@marvell.com>
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* Author: Shadi Ammouri <shadi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/resource.h>
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#include <linux/of_pci.h>
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#include <linux/of_irq.h>
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#include "pcie-designware.h"
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struct armada8k_pcie {
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struct pcie_port pp; /* pp.dbi_base is DT ctrl */
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struct clk *clk;
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};
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#define PCIE_VENDOR_REGS_OFFSET 0x8000
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#define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0)
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#define PCIE_APP_LTSSM_EN BIT(2)
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#define PCIE_DEVICE_TYPE_SHIFT 4
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#define PCIE_DEVICE_TYPE_MASK 0xF
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#define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */
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#define PCIE_GLOBAL_STATUS_REG (PCIE_VENDOR_REGS_OFFSET + 0x8)
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#define PCIE_GLB_STS_RDLH_LINK_UP BIT(1)
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#define PCIE_GLB_STS_PHY_LINK_UP BIT(9)
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#define PCIE_GLOBAL_INT_CAUSE1_REG (PCIE_VENDOR_REGS_OFFSET + 0x1C)
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#define PCIE_GLOBAL_INT_MASK1_REG (PCIE_VENDOR_REGS_OFFSET + 0x20)
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#define PCIE_INT_A_ASSERT_MASK BIT(9)
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#define PCIE_INT_B_ASSERT_MASK BIT(10)
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#define PCIE_INT_C_ASSERT_MASK BIT(11)
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#define PCIE_INT_D_ASSERT_MASK BIT(12)
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#define PCIE_ARCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x50)
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#define PCIE_AWCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x54)
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#define PCIE_ARUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x5C)
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#define PCIE_AWUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x60)
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/*
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* AR/AW Cache defauls: Normal memory, Write-Back, Read / Write
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* allocate
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*/
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#define ARCACHE_DEFAULT_VALUE 0x3511
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#define AWCACHE_DEFAULT_VALUE 0x5311
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#define DOMAIN_OUTER_SHAREABLE 0x2
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#define AX_USER_DOMAIN_MASK 0x3
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#define AX_USER_DOMAIN_SHIFT 4
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#define to_armada8k_pcie(x) container_of(x, struct armada8k_pcie, pp)
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static int armada8k_pcie_link_up(struct pcie_port *pp)
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{
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u32 reg;
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u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
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reg = dw_pcie_readl_rc(pp, PCIE_GLOBAL_STATUS_REG);
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if ((reg & mask) == mask)
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return 1;
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dev_dbg(pp->dev, "No link detected (Global-Status: 0x%08x).\n", reg);
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return 0;
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}
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static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie)
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{
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struct pcie_port *pp = &pcie->pp;
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u32 reg;
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if (!dw_pcie_link_up(pp)) {
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/* Disable LTSSM state machine to enable configuration */
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reg = dw_pcie_readl_rc(pp, PCIE_GLOBAL_CONTROL_REG);
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reg &= ~(PCIE_APP_LTSSM_EN);
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dw_pcie_writel_rc(pp, PCIE_GLOBAL_CONTROL_REG, reg);
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}
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/* Set the device to root complex mode */
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reg = dw_pcie_readl_rc(pp, PCIE_GLOBAL_CONTROL_REG);
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reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT);
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reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT;
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dw_pcie_writel_rc(pp, PCIE_GLOBAL_CONTROL_REG, reg);
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/* Set the PCIe master AxCache attributes */
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dw_pcie_writel_rc(pp, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE);
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dw_pcie_writel_rc(pp, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE);
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/* Set the PCIe master AxDomain attributes */
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reg = dw_pcie_readl_rc(pp, PCIE_ARUSER_REG);
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reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
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reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
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dw_pcie_writel_rc(pp, PCIE_ARUSER_REG, reg);
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reg = dw_pcie_readl_rc(pp, PCIE_AWUSER_REG);
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reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
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reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
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dw_pcie_writel_rc(pp, PCIE_AWUSER_REG, reg);
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/* Enable INT A-D interrupts */
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reg = dw_pcie_readl_rc(pp, PCIE_GLOBAL_INT_MASK1_REG);
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reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK |
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PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK;
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dw_pcie_writel_rc(pp, PCIE_GLOBAL_INT_MASK1_REG, reg);
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if (!dw_pcie_link_up(pp)) {
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/* Configuration done. Start LTSSM */
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reg = dw_pcie_readl_rc(pp, PCIE_GLOBAL_CONTROL_REG);
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reg |= PCIE_APP_LTSSM_EN;
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dw_pcie_writel_rc(pp, PCIE_GLOBAL_CONTROL_REG, reg);
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}
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/* Wait until the link becomes active again */
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if (dw_pcie_wait_for_link(pp))
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dev_err(pp->dev, "Link not up after reconfiguration\n");
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}
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static void armada8k_pcie_host_init(struct pcie_port *pp)
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{
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struct armada8k_pcie *pcie = to_armada8k_pcie(pp);
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dw_pcie_setup_rc(pp);
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armada8k_pcie_establish_link(pcie);
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}
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static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
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{
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struct armada8k_pcie *pcie = arg;
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struct pcie_port *pp = &pcie->pp;
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u32 val;
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/*
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* Interrupts are directly handled by the device driver of the
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* PCI device. However, they are also latched into the PCIe
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* controller, so we simply discard them.
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*/
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val = dw_pcie_readl_rc(pp, PCIE_GLOBAL_INT_CAUSE1_REG);
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dw_pcie_writel_rc(pp, PCIE_GLOBAL_INT_CAUSE1_REG, val);
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return IRQ_HANDLED;
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}
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static struct pcie_host_ops armada8k_pcie_host_ops = {
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.link_up = armada8k_pcie_link_up,
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.host_init = armada8k_pcie_host_init,
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};
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static int armada8k_add_pcie_port(struct armada8k_pcie *pcie,
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struct platform_device *pdev)
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{
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struct pcie_port *pp = &pcie->pp;
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struct device *dev = &pdev->dev;
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int ret;
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pp->root_bus_nr = -1;
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pp->ops = &armada8k_pcie_host_ops;
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pp->irq = platform_get_irq(pdev, 0);
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if (!pp->irq) {
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dev_err(dev, "failed to get irq for port\n");
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return -ENODEV;
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}
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ret = devm_request_irq(dev, pp->irq, armada8k_pcie_irq_handler,
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IRQF_SHARED, "armada8k-pcie", pcie);
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if (ret) {
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dev_err(dev, "failed to request irq %d\n", pp->irq);
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return ret;
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}
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ret = dw_pcie_host_init(pp);
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if (ret) {
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dev_err(dev, "failed to initialize host: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int armada8k_pcie_probe(struct platform_device *pdev)
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{
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struct armada8k_pcie *pcie;
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struct pcie_port *pp;
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struct device *dev = &pdev->dev;
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struct resource *base;
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int ret;
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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pcie->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(pcie->clk))
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return PTR_ERR(pcie->clk);
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clk_prepare_enable(pcie->clk);
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pp = &pcie->pp;
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pp->dev = dev;
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/* Get the dw-pcie unit configuration/control registers base. */
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base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
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pp->dbi_base = devm_ioremap_resource(dev, base);
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if (IS_ERR(pp->dbi_base)) {
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dev_err(dev, "couldn't remap regs base %p\n", base);
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ret = PTR_ERR(pp->dbi_base);
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goto fail;
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}
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ret = armada8k_add_pcie_port(pcie, pdev);
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if (ret)
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goto fail;
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return 0;
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fail:
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if (!IS_ERR(pcie->clk))
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clk_disable_unprepare(pcie->clk);
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return ret;
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}
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static const struct of_device_id armada8k_pcie_of_match[] = {
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{ .compatible = "marvell,armada8k-pcie", },
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{},
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};
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static struct platform_driver armada8k_pcie_driver = {
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.probe = armada8k_pcie_probe,
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.driver = {
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.name = "armada8k-pcie",
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.of_match_table = of_match_ptr(armada8k_pcie_of_match),
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},
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};
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builtin_platform_driver(armada8k_pcie_driver);
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