284 lines
7.5 KiB
C
284 lines
7.5 KiB
C
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/*
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* PCIe host controller driver for Axis ARTPEC-6 SoC
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*
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* Author: Niklas Cassel <niklas.cassel@axis.com>
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*
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* Based on work done by Phil Edworthy <phil@edworthys.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/resource.h>
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#include <linux/signal.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include "pcie-designware.h"
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#define to_artpec6_pcie(x) container_of(x, struct artpec6_pcie, pp)
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struct artpec6_pcie {
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struct pcie_port pp; /* pp.dbi_base is DT dbi */
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struct regmap *regmap; /* DT axis,syscon-pcie */
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void __iomem *phy_base; /* DT phy */
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};
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/* PCIe Port Logic registers (memory-mapped) */
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#define PL_OFFSET 0x700
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#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
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#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
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#define MISC_CONTROL_1_OFF (PL_OFFSET + 0x1bc)
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#define DBI_RO_WR_EN 1
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/* ARTPEC-6 specific registers */
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#define PCIECFG 0x18
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#define PCIECFG_DBG_OEN (1 << 24)
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#define PCIECFG_CORE_RESET_REQ (1 << 21)
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#define PCIECFG_LTSSM_ENABLE (1 << 20)
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#define PCIECFG_CLKREQ_B (1 << 11)
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#define PCIECFG_REFCLK_ENABLE (1 << 10)
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#define PCIECFG_PLL_ENABLE (1 << 9)
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#define PCIECFG_PCLK_ENABLE (1 << 8)
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#define PCIECFG_RISRCREN (1 << 4)
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#define PCIECFG_MODE_TX_DRV_EN (1 << 3)
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#define PCIECFG_CISRREN (1 << 2)
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#define PCIECFG_MACRO_ENABLE (1 << 0)
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#define NOCCFG 0x40
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#define NOCCFG_ENABLE_CLK_PCIE (1 << 4)
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#define NOCCFG_POWER_PCIE_IDLEACK (1 << 3)
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#define NOCCFG_POWER_PCIE_IDLE (1 << 2)
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#define NOCCFG_POWER_PCIE_IDLEREQ (1 << 1)
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#define PHY_STATUS 0x118
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#define PHY_COSPLLLOCK (1 << 0)
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#define ARTPEC6_CPU_TO_BUS_ADDR 0x0fffffff
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static u32 artpec6_pcie_readl(struct artpec6_pcie *artpec6_pcie, u32 offset)
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{
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u32 val;
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regmap_read(artpec6_pcie->regmap, offset, &val);
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return val;
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}
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static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u32 val)
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{
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regmap_write(artpec6_pcie->regmap, offset, val);
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}
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static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
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{
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struct pcie_port *pp = &artpec6_pcie->pp;
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u32 val;
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unsigned int retries;
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/* Hold DW core in reset */
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val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
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val |= PCIECFG_CORE_RESET_REQ;
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artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
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val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
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val |= PCIECFG_RISRCREN | /* Receiver term. 50 Ohm */
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PCIECFG_MODE_TX_DRV_EN |
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PCIECFG_CISRREN | /* Reference clock term. 100 Ohm */
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PCIECFG_MACRO_ENABLE;
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val |= PCIECFG_REFCLK_ENABLE;
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val &= ~PCIECFG_DBG_OEN;
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val &= ~PCIECFG_CLKREQ_B;
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artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
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usleep_range(5000, 6000);
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val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
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val |= NOCCFG_ENABLE_CLK_PCIE;
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artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
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usleep_range(20, 30);
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val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
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val |= PCIECFG_PCLK_ENABLE | PCIECFG_PLL_ENABLE;
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artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
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usleep_range(6000, 7000);
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val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
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val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
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artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
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retries = 50;
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do {
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usleep_range(1000, 2000);
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val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
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retries--;
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} while (retries &&
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(val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));
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retries = 50;
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do {
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usleep_range(1000, 2000);
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val = readl(artpec6_pcie->phy_base + PHY_STATUS);
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retries--;
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} while (retries && !(val & PHY_COSPLLLOCK));
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/* Take DW core out of reset */
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val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
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val &= ~PCIECFG_CORE_RESET_REQ;
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artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
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usleep_range(100, 200);
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/*
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* Enable writing to config regs. This is required as the Synopsys
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* driver changes the class code. That register needs DBI write enable.
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*/
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dw_pcie_writel_rc(pp, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
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pp->io_base &= ARTPEC6_CPU_TO_BUS_ADDR;
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pp->mem_base &= ARTPEC6_CPU_TO_BUS_ADDR;
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pp->cfg0_base &= ARTPEC6_CPU_TO_BUS_ADDR;
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pp->cfg1_base &= ARTPEC6_CPU_TO_BUS_ADDR;
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/* setup root complex */
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dw_pcie_setup_rc(pp);
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/* assert LTSSM enable */
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val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
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val |= PCIECFG_LTSSM_ENABLE;
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artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
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/* check if the link is up or not */
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if (!dw_pcie_wait_for_link(pp))
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return 0;
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dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
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dw_pcie_readl_rc(pp, PCIE_PHY_DEBUG_R0),
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dw_pcie_readl_rc(pp, PCIE_PHY_DEBUG_R1));
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return -ETIMEDOUT;
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}
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static void artpec6_pcie_enable_interrupts(struct artpec6_pcie *artpec6_pcie)
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{
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struct pcie_port *pp = &artpec6_pcie->pp;
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if (IS_ENABLED(CONFIG_PCI_MSI))
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dw_pcie_msi_init(pp);
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}
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static void artpec6_pcie_host_init(struct pcie_port *pp)
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{
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struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pp);
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artpec6_pcie_establish_link(artpec6_pcie);
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artpec6_pcie_enable_interrupts(artpec6_pcie);
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}
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static struct pcie_host_ops artpec6_pcie_host_ops = {
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.host_init = artpec6_pcie_host_init,
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};
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static irqreturn_t artpec6_pcie_msi_handler(int irq, void *arg)
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{
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struct artpec6_pcie *artpec6_pcie = arg;
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struct pcie_port *pp = &artpec6_pcie->pp;
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return dw_handle_msi_irq(pp);
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}
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static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
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struct platform_device *pdev)
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{
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struct pcie_port *pp = &artpec6_pcie->pp;
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struct device *dev = pp->dev;
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int ret;
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if (IS_ENABLED(CONFIG_PCI_MSI)) {
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pp->msi_irq = platform_get_irq_byname(pdev, "msi");
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if (pp->msi_irq <= 0) {
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dev_err(dev, "failed to get MSI irq\n");
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return -ENODEV;
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}
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ret = devm_request_irq(dev, pp->msi_irq,
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artpec6_pcie_msi_handler,
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IRQF_SHARED | IRQF_NO_THREAD,
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"artpec6-pcie-msi", artpec6_pcie);
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if (ret) {
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dev_err(dev, "failed to request MSI irq\n");
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return ret;
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}
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}
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pp->root_bus_nr = -1;
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pp->ops = &artpec6_pcie_host_ops;
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ret = dw_pcie_host_init(pp);
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if (ret) {
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dev_err(dev, "failed to initialize host\n");
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return ret;
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}
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return 0;
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}
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static int artpec6_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct artpec6_pcie *artpec6_pcie;
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struct pcie_port *pp;
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struct resource *dbi_base;
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struct resource *phy_base;
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int ret;
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artpec6_pcie = devm_kzalloc(dev, sizeof(*artpec6_pcie), GFP_KERNEL);
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if (!artpec6_pcie)
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return -ENOMEM;
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pp = &artpec6_pcie->pp;
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pp->dev = dev;
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dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
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pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
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if (IS_ERR(pp->dbi_base))
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return PTR_ERR(pp->dbi_base);
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phy_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
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artpec6_pcie->phy_base = devm_ioremap_resource(dev, phy_base);
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if (IS_ERR(artpec6_pcie->phy_base))
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return PTR_ERR(artpec6_pcie->phy_base);
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artpec6_pcie->regmap =
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syscon_regmap_lookup_by_phandle(dev->of_node,
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"axis,syscon-pcie");
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if (IS_ERR(artpec6_pcie->regmap))
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return PTR_ERR(artpec6_pcie->regmap);
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ret = artpec6_add_pcie_port(artpec6_pcie, pdev);
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if (ret < 0)
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return ret;
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return 0;
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}
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static const struct of_device_id artpec6_pcie_of_match[] = {
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{ .compatible = "axis,artpec6-pcie", },
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{},
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};
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static struct platform_driver artpec6_pcie_driver = {
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.probe = artpec6_pcie_probe,
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.driver = {
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.name = "artpec6-pcie",
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.of_match_table = artpec6_pcie_of_match,
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},
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};
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builtin_platform_driver(artpec6_pcie_driver);
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