304 lines
7.6 KiB
C
304 lines
7.6 KiB
C
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/*
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* PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
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*
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* SPEAr13xx PCIe Glue Layer Source Code
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*
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* Copyright (C) 2010-2014 ST Microelectronics
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* Pratyush Anand <pratyush.anand@gmail.com>
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* Mohit Kumar <mohit.kumar.dhaka@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/resource.h>
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#include "pcie-designware.h"
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struct spear13xx_pcie {
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struct pcie_port pp; /* DT dbi is pp.dbi_base */
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void __iomem *app_base;
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struct phy *phy;
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struct clk *clk;
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bool is_gen1;
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};
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struct pcie_app_reg {
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u32 app_ctrl_0; /* cr0 */
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u32 app_ctrl_1; /* cr1 */
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u32 app_status_0; /* cr2 */
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u32 app_status_1; /* cr3 */
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u32 msg_status; /* cr4 */
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u32 msg_payload; /* cr5 */
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u32 int_sts; /* cr6 */
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u32 int_clr; /* cr7 */
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u32 int_mask; /* cr8 */
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u32 mst_bmisc; /* cr9 */
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u32 phy_ctrl; /* cr10 */
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u32 phy_status; /* cr11 */
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u32 cxpl_debug_info_0; /* cr12 */
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u32 cxpl_debug_info_1; /* cr13 */
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u32 ven_msg_ctrl_0; /* cr14 */
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u32 ven_msg_ctrl_1; /* cr15 */
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u32 ven_msg_data_0; /* cr16 */
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u32 ven_msg_data_1; /* cr17 */
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u32 ven_msi_0; /* cr18 */
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u32 ven_msi_1; /* cr19 */
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u32 mst_rmisc; /* cr20 */
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};
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/* CR0 ID */
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#define APP_LTSSM_ENABLE_ID 3
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#define DEVICE_TYPE_RC (4 << 25)
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#define MISCTRL_EN_ID 30
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#define REG_TRANSLATION_ENABLE 31
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/* CR3 ID */
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#define XMLH_LINK_UP (1 << 6)
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/* CR6 */
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#define MSI_CTRL_INT (1 << 26)
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#define EXP_CAP_ID_OFFSET 0x70
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#define to_spear13xx_pcie(x) container_of(x, struct spear13xx_pcie, pp)
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static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
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{
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struct pcie_port *pp = &spear13xx_pcie->pp;
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struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
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u32 val;
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u32 exp_cap_off = EXP_CAP_ID_OFFSET;
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if (dw_pcie_link_up(pp)) {
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dev_err(pp->dev, "link already up\n");
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return 0;
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}
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dw_pcie_setup_rc(pp);
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/*
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* this controller support only 128 bytes read size, however its
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* default value in capability register is 512 bytes. So force
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* it to 128 here.
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*/
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dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val);
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val &= ~PCI_EXP_DEVCTL_READRQ;
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dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val);
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dw_pcie_cfg_write(pp->dbi_base + PCI_VENDOR_ID, 2, 0x104A);
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dw_pcie_cfg_write(pp->dbi_base + PCI_DEVICE_ID, 2, 0xCD80);
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/*
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* if is_gen1 is set then handle it, so that some buggy card
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* also works
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*/
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if (spear13xx_pcie->is_gen1) {
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dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
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4, &val);
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if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
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val &= ~((u32)PCI_EXP_LNKCAP_SLS);
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val |= PCI_EXP_LNKCAP_SLS_2_5GB;
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dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +
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PCI_EXP_LNKCAP, 4, val);
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}
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dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
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2, &val);
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if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
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val &= ~((u32)PCI_EXP_LNKCAP_SLS);
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val |= PCI_EXP_LNKCAP_SLS_2_5GB;
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dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +
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PCI_EXP_LNKCTL2, 2, val);
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}
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}
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/* enable ltssm */
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writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
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| (1 << APP_LTSSM_ENABLE_ID)
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| ((u32)1 << REG_TRANSLATION_ENABLE),
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&app_reg->app_ctrl_0);
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return dw_pcie_wait_for_link(pp);
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}
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static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
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{
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struct spear13xx_pcie *spear13xx_pcie = arg;
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struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
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struct pcie_port *pp = &spear13xx_pcie->pp;
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unsigned int status;
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status = readl(&app_reg->int_sts);
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if (status & MSI_CTRL_INT) {
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BUG_ON(!IS_ENABLED(CONFIG_PCI_MSI));
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dw_handle_msi_irq(pp);
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}
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writel(status, &app_reg->int_clr);
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return IRQ_HANDLED;
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}
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static void spear13xx_pcie_enable_interrupts(struct spear13xx_pcie *spear13xx_pcie)
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{
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struct pcie_port *pp = &spear13xx_pcie->pp;
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struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
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/* Enable MSI interrupt */
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if (IS_ENABLED(CONFIG_PCI_MSI)) {
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dw_pcie_msi_init(pp);
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writel(readl(&app_reg->int_mask) |
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MSI_CTRL_INT, &app_reg->int_mask);
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}
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}
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static int spear13xx_pcie_link_up(struct pcie_port *pp)
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{
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struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
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struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
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if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
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return 1;
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return 0;
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}
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static void spear13xx_pcie_host_init(struct pcie_port *pp)
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{
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struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
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spear13xx_pcie_establish_link(spear13xx_pcie);
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spear13xx_pcie_enable_interrupts(spear13xx_pcie);
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}
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static struct pcie_host_ops spear13xx_pcie_host_ops = {
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.link_up = spear13xx_pcie_link_up,
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.host_init = spear13xx_pcie_host_init,
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};
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static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie,
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struct platform_device *pdev)
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{
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struct pcie_port *pp = &spear13xx_pcie->pp;
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struct device *dev = pp->dev;
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int ret;
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pp->irq = platform_get_irq(pdev, 0);
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if (!pp->irq) {
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dev_err(dev, "failed to get irq\n");
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return -ENODEV;
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}
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ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
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IRQF_SHARED | IRQF_NO_THREAD,
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"spear1340-pcie", spear13xx_pcie);
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if (ret) {
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dev_err(dev, "failed to request irq %d\n", pp->irq);
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return ret;
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}
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pp->root_bus_nr = -1;
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pp->ops = &spear13xx_pcie_host_ops;
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ret = dw_pcie_host_init(pp);
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if (ret) {
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dev_err(dev, "failed to initialize host\n");
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return ret;
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}
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return 0;
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}
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static int spear13xx_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct spear13xx_pcie *spear13xx_pcie;
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struct pcie_port *pp;
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struct device_node *np = dev->of_node;
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struct resource *dbi_base;
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int ret;
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spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
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if (!spear13xx_pcie)
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return -ENOMEM;
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spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
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if (IS_ERR(spear13xx_pcie->phy)) {
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ret = PTR_ERR(spear13xx_pcie->phy);
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if (ret == -EPROBE_DEFER)
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dev_info(dev, "probe deferred\n");
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else
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dev_err(dev, "couldn't get pcie-phy\n");
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return ret;
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}
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phy_init(spear13xx_pcie->phy);
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spear13xx_pcie->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(spear13xx_pcie->clk)) {
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dev_err(dev, "couldn't get clk for pcie\n");
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return PTR_ERR(spear13xx_pcie->clk);
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}
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ret = clk_prepare_enable(spear13xx_pcie->clk);
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if (ret) {
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dev_err(dev, "couldn't enable clk for pcie\n");
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return ret;
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}
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pp = &spear13xx_pcie->pp;
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pp->dev = dev;
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dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
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pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
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if (IS_ERR(pp->dbi_base)) {
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dev_err(dev, "couldn't remap dbi base %p\n", dbi_base);
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ret = PTR_ERR(pp->dbi_base);
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goto fail_clk;
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}
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spear13xx_pcie->app_base = pp->dbi_base + 0x2000;
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if (of_property_read_bool(np, "st,pcie-is-gen1"))
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spear13xx_pcie->is_gen1 = true;
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ret = spear13xx_add_pcie_port(spear13xx_pcie, pdev);
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if (ret < 0)
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goto fail_clk;
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platform_set_drvdata(pdev, spear13xx_pcie);
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return 0;
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fail_clk:
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clk_disable_unprepare(spear13xx_pcie->clk);
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return ret;
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}
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static const struct of_device_id spear13xx_pcie_of_match[] = {
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{ .compatible = "st,spear1340-pcie", },
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{},
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};
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static struct platform_driver spear13xx_pcie_driver = {
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.probe = spear13xx_pcie_probe,
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.driver = {
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.name = "spear-pcie",
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.of_match_table = of_match_ptr(spear13xx_pcie_of_match),
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},
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};
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static int __init spear13xx_pcie_init(void)
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{
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return platform_driver_register(&spear13xx_pcie_driver);
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}
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device_initcall(spear13xx_pcie_init);
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