349 lines
11 KiB
C
349 lines
11 KiB
C
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/*
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* Standard Hot Plug Controller Driver
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*
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* Copyright (C) 1995,2001 Compaq Computer Corporation
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* Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
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* Copyright (C) 2001 IBM
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* Copyright (C) 2003-2004 Intel Corporation
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*
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
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*
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*/
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#ifndef _SHPCHP_H
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#define _SHPCHP_H
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/pci_hotplug.h>
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#include <linux/delay.h>
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#include <linux/sched.h> /* signal_pending(), struct timer_list */
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#include <linux/mutex.h>
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#include <linux/workqueue.h>
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#if !defined(MODULE)
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#define MY_NAME "shpchp"
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#else
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#define MY_NAME THIS_MODULE->name
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#endif
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extern bool shpchp_poll_mode;
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extern int shpchp_poll_time;
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extern bool shpchp_debug;
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#define dbg(format, arg...) \
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do { \
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if (shpchp_debug) \
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printk(KERN_DEBUG "%s: " format, MY_NAME, ## arg); \
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} while (0)
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#define err(format, arg...) \
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printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
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#define info(format, arg...) \
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printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
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#define warn(format, arg...) \
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printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
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#define ctrl_dbg(ctrl, format, arg...) \
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do { \
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if (shpchp_debug) \
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dev_printk(KERN_DEBUG, &ctrl->pci_dev->dev, \
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format, ## arg); \
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} while (0)
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#define ctrl_err(ctrl, format, arg...) \
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dev_err(&ctrl->pci_dev->dev, format, ## arg)
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#define ctrl_info(ctrl, format, arg...) \
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dev_info(&ctrl->pci_dev->dev, format, ## arg)
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#define ctrl_warn(ctrl, format, arg...) \
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dev_warn(&ctrl->pci_dev->dev, format, ## arg)
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#define SLOT_NAME_SIZE 10
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struct slot {
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u8 bus;
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u8 device;
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u16 status;
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u32 number;
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u8 is_a_board;
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u8 state;
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u8 presence_save;
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u8 pwr_save;
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struct controller *ctrl;
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const struct hpc_ops *hpc_ops;
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struct hotplug_slot *hotplug_slot;
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struct list_head slot_list;
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struct delayed_work work; /* work for button event */
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struct mutex lock;
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struct workqueue_struct *wq;
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u8 hp_slot;
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};
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struct event_info {
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u32 event_type;
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struct slot *p_slot;
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struct work_struct work;
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};
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struct controller {
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struct mutex crit_sect; /* critical section mutex */
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struct mutex cmd_lock; /* command lock */
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int num_slots; /* Number of slots on ctlr */
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int slot_num_inc; /* 1 or -1 */
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struct pci_dev *pci_dev;
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struct list_head slot_list;
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const struct hpc_ops *hpc_ops;
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wait_queue_head_t queue; /* sleep & wake process */
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u8 slot_device_offset;
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u32 pcix_misc2_reg; /* for amd pogo errata */
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u32 first_slot; /* First physical slot number */
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u32 cap_offset;
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unsigned long mmio_base;
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unsigned long mmio_size;
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void __iomem *creg;
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struct timer_list poll_timer;
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};
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/* Define AMD SHPC ID */
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#define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450
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#define PCI_DEVICE_ID_AMD_POGO_7458 0x7458
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/* AMD PCI-X bridge registers */
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#define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C
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#define PCIX_MISCII_OFFSET 0x48
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#define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80
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/* AMD PCIX_MISCII masks and offsets */
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#define PERRNONFATALENABLE_MASK 0x00040000
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#define PERRFATALENABLE_MASK 0x00080000
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#define PERRFLOODENABLE_MASK 0x00100000
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#define SERRNONFATALENABLE_MASK 0x00200000
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#define SERRFATALENABLE_MASK 0x00400000
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/* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
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#define PERR_OBSERVED_MASK 0x00000001
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/* AMD PCIX_MEM_BASE_LIMIT masks */
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#define RSE_MASK 0x40000000
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#define INT_BUTTON_IGNORE 0
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#define INT_PRESENCE_ON 1
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#define INT_PRESENCE_OFF 2
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#define INT_SWITCH_CLOSE 3
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#define INT_SWITCH_OPEN 4
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#define INT_POWER_FAULT 5
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#define INT_POWER_FAULT_CLEAR 6
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#define INT_BUTTON_PRESS 7
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#define INT_BUTTON_RELEASE 8
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#define INT_BUTTON_CANCEL 9
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#define STATIC_STATE 0
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#define BLINKINGON_STATE 1
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#define BLINKINGOFF_STATE 2
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#define POWERON_STATE 3
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#define POWEROFF_STATE 4
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/* Error messages */
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#define INTERLOCK_OPEN 0x00000002
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#define ADD_NOT_SUPPORTED 0x00000003
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#define CARD_FUNCTIONING 0x00000005
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#define ADAPTER_NOT_SAME 0x00000006
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#define NO_ADAPTER_PRESENT 0x00000009
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#define NOT_ENOUGH_RESOURCES 0x0000000B
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#define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C
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#define WRONG_BUS_FREQUENCY 0x0000000D
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#define POWER_FAILURE 0x0000000E
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int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
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void shpchp_remove_ctrl_files(struct controller *ctrl);
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int shpchp_sysfs_enable_slot(struct slot *slot);
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int shpchp_sysfs_disable_slot(struct slot *slot);
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u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
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u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
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u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
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u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
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int shpchp_configure_device(struct slot *p_slot);
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int shpchp_unconfigure_device(struct slot *p_slot);
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void cleanup_slots(struct controller *ctrl);
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void shpchp_queue_pushbutton_work(struct work_struct *work);
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int shpc_init(struct controller *ctrl, struct pci_dev *pdev);
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static inline const char *slot_name(struct slot *slot)
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{
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return hotplug_slot_name(slot->hotplug_slot);
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}
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#ifdef CONFIG_ACPI
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#include <linux/pci-acpi.h>
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static inline int get_hp_hw_control_from_firmware(struct pci_dev *dev)
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{
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u32 flags = OSC_PCI_SHPC_NATIVE_HP_CONTROL;
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return acpi_get_hp_hw_control_from_firmware(dev, flags);
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}
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#else
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#define get_hp_hw_control_from_firmware(dev) (0)
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#endif
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struct ctrl_reg {
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volatile u32 base_offset;
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volatile u32 slot_avail1;
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volatile u32 slot_avail2;
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volatile u32 slot_config;
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volatile u16 sec_bus_config;
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volatile u8 msi_ctrl;
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volatile u8 prog_interface;
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volatile u16 cmd;
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volatile u16 cmd_status;
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volatile u32 intr_loc;
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volatile u32 serr_loc;
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volatile u32 serr_intr_enable;
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volatile u32 slot1;
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} __attribute__ ((packed));
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/* offsets to the controller registers based on the above structure layout */
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enum ctrl_offsets {
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BASE_OFFSET = offsetof(struct ctrl_reg, base_offset),
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SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
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SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
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SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
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SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
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MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
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PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
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CMD = offsetof(struct ctrl_reg, cmd),
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CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),
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INTR_LOC = offsetof(struct ctrl_reg, intr_loc),
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SERR_LOC = offsetof(struct ctrl_reg, serr_loc),
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SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
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SLOT1 = offsetof(struct ctrl_reg, slot1),
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};
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static inline struct slot *get_slot(struct hotplug_slot *hotplug_slot)
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{
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return hotplug_slot->private;
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}
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static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)
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{
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struct slot *slot;
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list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
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if (slot->device == device)
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return slot;
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}
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ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);
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return NULL;
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}
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static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
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{
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u32 pcix_misc2_temp;
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/* save MiscII register */
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pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
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p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
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/* clear SERR/PERR enable bits */
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pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
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pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
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pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
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pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
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pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
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pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
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}
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static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
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{
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u32 pcix_misc2_temp;
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u32 pcix_bridge_errors_reg;
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u32 pcix_mem_base_reg;
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u8 perr_set;
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u8 rse_set;
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/* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
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pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
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perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
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if (perr_set) {
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ctrl_dbg(p_slot->ctrl,
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"Bridge_Errors[ PERR_OBSERVED = %08X] (W1C)\n",
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perr_set);
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pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
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}
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/* write-one-to-clear Memory_Base_Limit[ RSE ] */
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pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
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rse_set = pcix_mem_base_reg & RSE_MASK;
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if (rse_set) {
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ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");
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pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
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}
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/* restore MiscII register */
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pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
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if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
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pcix_misc2_temp |= SERRFATALENABLE_MASK;
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else
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pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
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if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
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pcix_misc2_temp |= SERRNONFATALENABLE_MASK;
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else
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pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
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if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
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pcix_misc2_temp |= PERRFLOODENABLE_MASK;
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else
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pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
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if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
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pcix_misc2_temp |= PERRFATALENABLE_MASK;
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else
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pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
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if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
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pcix_misc2_temp |= PERRNONFATALENABLE_MASK;
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else
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pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
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pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
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}
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struct hpc_ops {
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int (*power_on_slot)(struct slot *slot);
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int (*slot_enable)(struct slot *slot);
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int (*slot_disable)(struct slot *slot);
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int (*set_bus_speed_mode)(struct slot *slot, enum pci_bus_speed speed);
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int (*get_power_status)(struct slot *slot, u8 *status);
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int (*get_attention_status)(struct slot *slot, u8 *status);
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int (*set_attention_status)(struct slot *slot, u8 status);
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int (*get_latch_status)(struct slot *slot, u8 *status);
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int (*get_adapter_status)(struct slot *slot, u8 *status);
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int (*get_adapter_speed)(struct slot *slot, enum pci_bus_speed *speed);
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int (*get_mode1_ECC_cap)(struct slot *slot, u8 *mode);
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int (*get_prog_int)(struct slot *slot, u8 *prog_int);
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int (*query_power_fault)(struct slot *slot);
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void (*green_led_on)(struct slot *slot);
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void (*green_led_off)(struct slot *slot);
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void (*green_led_blink)(struct slot *slot);
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void (*release_ctlr)(struct controller *ctrl);
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int (*check_cmd_status)(struct controller *ctrl);
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};
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#endif /* _SHPCHP_H */
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