346 lines
9.5 KiB
C
346 lines
9.5 KiB
C
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/*
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* Copyright (C) 2014 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/math64.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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/*
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* The Kona PWM has some unusual characteristics. Here are the main points.
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*
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* 1) There is no disable bit and the hardware docs advise programming a zero
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* duty to achieve output equivalent to that of a normal disable operation.
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*
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* 2) Changes to prescale, duty, period, and polarity do not take effect until
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* a subsequent rising edge of the trigger bit.
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*
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* 3) If the smooth bit and trigger bit are both low, the output is a constant
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* high signal. Otherwise, the earlier waveform continues to be output.
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*
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* 4) If the smooth bit is set on the rising edge of the trigger bit, output
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* will transition to the new settings on a period boundary (which could be
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* seconds away). If the smooth bit is clear, new settings will be applied
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* as soon as possible (the hardware always has a 400ns delay).
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*
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* 5) When the external clock that feeds the PWM is disabled, output is pegged
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* high or low depending on its state at that exact instant.
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*/
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#define PWM_CONTROL_OFFSET (0x00000000)
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#define PWM_CONTROL_SMOOTH_SHIFT(chan) (24 + (chan))
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#define PWM_CONTROL_TYPE_SHIFT(chan) (16 + (chan))
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#define PWM_CONTROL_POLARITY_SHIFT(chan) (8 + (chan))
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#define PWM_CONTROL_TRIGGER_SHIFT(chan) (chan)
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#define PRESCALE_OFFSET (0x00000004)
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#define PRESCALE_SHIFT(chan) ((chan) << 2)
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#define PRESCALE_MASK(chan) (0x7 << PRESCALE_SHIFT(chan))
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#define PRESCALE_MIN (0x00000000)
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#define PRESCALE_MAX (0x00000007)
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#define PERIOD_COUNT_OFFSET(chan) (0x00000008 + ((chan) << 3))
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#define PERIOD_COUNT_MIN (0x00000002)
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#define PERIOD_COUNT_MAX (0x00ffffff)
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#define DUTY_CYCLE_HIGH_OFFSET(chan) (0x0000000c + ((chan) << 3))
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#define DUTY_CYCLE_HIGH_MIN (0x00000000)
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#define DUTY_CYCLE_HIGH_MAX (0x00ffffff)
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struct kona_pwmc {
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struct pwm_chip chip;
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void __iomem *base;
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struct clk *clk;
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};
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static inline struct kona_pwmc *to_kona_pwmc(struct pwm_chip *_chip)
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{
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return container_of(_chip, struct kona_pwmc, chip);
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}
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/*
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* Clear trigger bit but set smooth bit to maintain old output.
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*/
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static void kona_pwmc_prepare_for_settings(struct kona_pwmc *kp,
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unsigned int chan)
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{
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unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
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value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
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value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan));
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writel(value, kp->base + PWM_CONTROL_OFFSET);
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/*
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* There must be a min 400ns delay between clearing trigger and setting
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* it. Failing to do this may result in no PWM signal.
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*/
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ndelay(400);
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}
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static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int chan)
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{
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unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
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/* Set trigger bit and clear smooth bit to apply new settings */
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value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
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value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
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writel(value, kp->base + PWM_CONTROL_OFFSET);
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/* Trigger bit must be held high for at least 400 ns. */
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ndelay(400);
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}
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static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct kona_pwmc *kp = to_kona_pwmc(chip);
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u64 val, div, rate;
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unsigned long prescale = PRESCALE_MIN, pc, dc;
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unsigned int value, chan = pwm->hwpwm;
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/*
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* Find period count, duty count and prescale to suit duty_ns and
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* period_ns. This is done according to formulas described below:
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*
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* period_ns = 10^9 * (PRESCALE + 1) * PC / PWM_CLK_RATE
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* duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
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*
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* PC = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
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* DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
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*/
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rate = clk_get_rate(kp->clk);
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while (1) {
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div = 1000000000;
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div *= 1 + prescale;
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val = rate * period_ns;
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pc = div64_u64(val, div);
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val = rate * duty_ns;
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dc = div64_u64(val, div);
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/* If duty_ns or period_ns are not achievable then return */
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if (pc < PERIOD_COUNT_MIN || dc < DUTY_CYCLE_HIGH_MIN)
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return -EINVAL;
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/* If pc and dc are in bounds, the calculation is done */
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if (pc <= PERIOD_COUNT_MAX && dc <= DUTY_CYCLE_HIGH_MAX)
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break;
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/* Otherwise, increase prescale and recalculate pc and dc */
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if (++prescale > PRESCALE_MAX)
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return -EINVAL;
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}
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/*
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* Don't apply settings if disabled. The period and duty cycle are
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* always calculated above to ensure the new values are
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* validated immediately instead of on enable.
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*/
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if (pwm_is_enabled(pwm)) {
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kona_pwmc_prepare_for_settings(kp, chan);
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value = readl(kp->base + PRESCALE_OFFSET);
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value &= ~PRESCALE_MASK(chan);
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value |= prescale << PRESCALE_SHIFT(chan);
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writel(value, kp->base + PRESCALE_OFFSET);
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writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
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writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
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kona_pwmc_apply_settings(kp, chan);
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}
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return 0;
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}
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static int kona_pwmc_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
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enum pwm_polarity polarity)
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{
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struct kona_pwmc *kp = to_kona_pwmc(chip);
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unsigned int chan = pwm->hwpwm;
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unsigned int value;
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int ret;
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ret = clk_prepare_enable(kp->clk);
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if (ret < 0) {
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dev_err(chip->dev, "failed to enable clock: %d\n", ret);
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return ret;
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}
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kona_pwmc_prepare_for_settings(kp, chan);
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value = readl(kp->base + PWM_CONTROL_OFFSET);
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if (polarity == PWM_POLARITY_NORMAL)
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value |= 1 << PWM_CONTROL_POLARITY_SHIFT(chan);
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else
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value &= ~(1 << PWM_CONTROL_POLARITY_SHIFT(chan));
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writel(value, kp->base + PWM_CONTROL_OFFSET);
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kona_pwmc_apply_settings(kp, chan);
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clk_disable_unprepare(kp->clk);
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return 0;
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}
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static int kona_pwmc_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct kona_pwmc *kp = to_kona_pwmc(chip);
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int ret;
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ret = clk_prepare_enable(kp->clk);
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if (ret < 0) {
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dev_err(chip->dev, "failed to enable clock: %d\n", ret);
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return ret;
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}
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ret = kona_pwmc_config(chip, pwm, pwm_get_duty_cycle(pwm),
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pwm_get_period(pwm));
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if (ret < 0) {
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clk_disable_unprepare(kp->clk);
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return ret;
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}
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return 0;
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}
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static void kona_pwmc_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct kona_pwmc *kp = to_kona_pwmc(chip);
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unsigned int chan = pwm->hwpwm;
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unsigned int value;
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kona_pwmc_prepare_for_settings(kp, chan);
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/* Simulate a disable by configuring for zero duty */
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writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
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writel(0, kp->base + PERIOD_COUNT_OFFSET(chan));
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/* Set prescale to 0 for this channel */
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value = readl(kp->base + PRESCALE_OFFSET);
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value &= ~PRESCALE_MASK(chan);
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writel(value, kp->base + PRESCALE_OFFSET);
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kona_pwmc_apply_settings(kp, chan);
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clk_disable_unprepare(kp->clk);
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}
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static const struct pwm_ops kona_pwm_ops = {
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.config = kona_pwmc_config,
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.set_polarity = kona_pwmc_set_polarity,
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.enable = kona_pwmc_enable,
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.disable = kona_pwmc_disable,
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.owner = THIS_MODULE,
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};
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static int kona_pwmc_probe(struct platform_device *pdev)
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{
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struct kona_pwmc *kp;
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struct resource *res;
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unsigned int chan;
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unsigned int value = 0;
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int ret = 0;
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kp = devm_kzalloc(&pdev->dev, sizeof(*kp), GFP_KERNEL);
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if (kp == NULL)
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return -ENOMEM;
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platform_set_drvdata(pdev, kp);
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kp->chip.dev = &pdev->dev;
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kp->chip.ops = &kona_pwm_ops;
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kp->chip.base = -1;
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kp->chip.npwm = 6;
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kp->chip.of_xlate = of_pwm_xlate_with_flags;
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kp->chip.of_pwm_n_cells = 3;
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kp->chip.can_sleep = true;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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kp->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(kp->base))
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return PTR_ERR(kp->base);
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kp->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(kp->clk)) {
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dev_err(&pdev->dev, "failed to get clock: %ld\n",
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PTR_ERR(kp->clk));
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return PTR_ERR(kp->clk);
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}
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ret = clk_prepare_enable(kp->clk);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
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return ret;
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}
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/* Set push/pull for all channels */
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for (chan = 0; chan < kp->chip.npwm; chan++)
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value |= (1 << PWM_CONTROL_TYPE_SHIFT(chan));
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writel(value, kp->base + PWM_CONTROL_OFFSET);
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clk_disable_unprepare(kp->clk);
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ret = pwmchip_add_with_polarity(&kp->chip, PWM_POLARITY_INVERSED);
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if (ret < 0)
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dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
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return ret;
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}
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static int kona_pwmc_remove(struct platform_device *pdev)
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{
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struct kona_pwmc *kp = platform_get_drvdata(pdev);
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unsigned int chan;
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for (chan = 0; chan < kp->chip.npwm; chan++)
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if (pwm_is_enabled(&kp->chip.pwms[chan]))
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clk_disable_unprepare(kp->clk);
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return pwmchip_remove(&kp->chip);
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}
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static const struct of_device_id bcm_kona_pwmc_dt[] = {
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{ .compatible = "brcm,kona-pwm" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, bcm_kona_pwmc_dt);
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static struct platform_driver kona_pwmc_driver = {
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.driver = {
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.name = "bcm-kona-pwm",
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.of_match_table = bcm_kona_pwmc_dt,
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},
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.probe = kona_pwmc_probe,
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.remove = kona_pwmc_remove,
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};
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module_platform_driver(kona_pwmc_driver);
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MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>");
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MODULE_AUTHOR("Tim Kryger <tkryger@broadcom.com>");
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MODULE_DESCRIPTION("Broadcom Kona PWM driver");
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MODULE_LICENSE("GPL v2");
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