122 lines
3.8 KiB
C
122 lines
3.8 KiB
C
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/*
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* This file is part of the Chelsio FCoE driver for Linux.
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*
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* Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __CSIO_HW_CHIP_H__
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#define __CSIO_HW_CHIP_H__
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#include "csio_defs.h"
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/* Define MACRO values */
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#define CSIO_HW_T5 0x5000
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#define CSIO_T5_FCOE_ASIC 0x5600
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#define CSIO_HW_CHIP_MASK 0xF000
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#define T5_REGMAP_SIZE (332 * 1024)
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#define FW_FNAME_T5 "cxgb4/t5fw.bin"
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#define FW_CFG_NAME_T5 "cxgb4/t5-config.txt"
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#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
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#define CHELSIO_CHIP_FPGA 0x100
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#define CHELSIO_CHIP_VERSION(code) (((code) >> 12) & 0xf)
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#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
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#define CHELSIO_T5 0x5
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enum chip_type {
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T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
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T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
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T5_FIRST_REV = T5_A0,
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T5_LAST_REV = T5_A1,
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};
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static inline int csio_is_t5(uint16_t chip)
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{
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return (chip == CSIO_HW_T5);
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}
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/* Define MACRO DEFINITIONS */
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#define CSIO_DEVICE(devid, idx) \
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{ PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) }
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#include "t4fw_api.h"
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#include "t4fw_version.h"
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#define FW_VERSION(chip) ( \
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FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
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FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
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FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
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FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
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#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
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struct fw_info {
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u8 chip;
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char *fs_name;
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char *fw_mod_name;
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struct fw_hdr fw_hdr;
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};
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/* Declare ENUMS */
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enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
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enum {
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MEMWIN_APERTURE = 2048,
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MEMWIN_BASE = 0x1b800,
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};
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/* Slow path handlers */
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struct intr_info {
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unsigned int mask; /* bits to check in interrupt status */
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const char *msg; /* message to print or NULL */
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short stat_idx; /* stat counter to increment or -1 */
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unsigned short fatal; /* whether the condition reported is fatal */
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};
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/* T4/T5 Chip specific ops */
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struct csio_hw;
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struct csio_hw_chip_ops {
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int (*chip_set_mem_win)(struct csio_hw *, uint32_t);
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void (*chip_pcie_intr_handler)(struct csio_hw *);
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uint32_t (*chip_flash_cfg_addr)(struct csio_hw *);
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int (*chip_mc_read)(struct csio_hw *, int, uint32_t,
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__be32 *, uint64_t *);
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int (*chip_edc_read)(struct csio_hw *, int, uint32_t,
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__be32 *, uint64_t *);
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int (*chip_memory_rw)(struct csio_hw *, u32, int, u32,
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u32, uint32_t *, int);
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void (*chip_dfs_create_ext_mem)(struct csio_hw *);
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};
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extern struct csio_hw_chip_ops t5_ops;
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#endif /* #ifndef __CSIO_HW_CHIP_H__ */
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