427 lines
11 KiB
C
427 lines
11 KiB
C
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/*
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* R-Car SYSC Power management support
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*
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* Copyright (C) 2014 Magnus Damm
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* Copyright (C) 2015-2016 Glider bvba
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/clk/renesas.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/mm.h>
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#include <linux/of_address.h>
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#include <linux/pm_domain.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/soc/renesas/rcar-sysc.h>
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#include "rcar-sysc.h"
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/* SYSC Common */
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#define SYSCSR 0x00 /* SYSC Status Register */
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#define SYSCISR 0x04 /* Interrupt Status Register */
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#define SYSCISCR 0x08 /* Interrupt Status Clear Register */
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#define SYSCIER 0x0c /* Interrupt Enable Register */
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#define SYSCIMR 0x10 /* Interrupt Mask Register */
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/* SYSC Status Register */
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#define SYSCSR_PONENB 1 /* Ready for power resume requests */
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#define SYSCSR_POFFENB 0 /* Ready for power shutoff requests */
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/*
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* Power Control Register Offsets inside the register block for each domain
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* Note: The "CR" registers for ARM cores exist on H1 only
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* Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2
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* Use PSCI on R-Car Gen3
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*/
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#define PWRSR_OFFS 0x00 /* Power Status Register */
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#define PWROFFCR_OFFS 0x04 /* Power Shutoff Control Register */
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#define PWROFFSR_OFFS 0x08 /* Power Shutoff Status Register */
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#define PWRONCR_OFFS 0x0c /* Power Resume Control Register */
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#define PWRONSR_OFFS 0x10 /* Power Resume Status Register */
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#define PWRER_OFFS 0x14 /* Power Shutoff/Resume Error */
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#define SYSCSR_RETRIES 100
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#define SYSCSR_DELAY_US 1
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#define PWRER_RETRIES 100
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#define PWRER_DELAY_US 1
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#define SYSCISR_RETRIES 1000
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#define SYSCISR_DELAY_US 1
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#define RCAR_PD_ALWAYS_ON 32 /* Always-on power area */
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static void __iomem *rcar_sysc_base;
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static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
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static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on)
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{
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unsigned int sr_bit, reg_offs;
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int k;
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if (on) {
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sr_bit = SYSCSR_PONENB;
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reg_offs = PWRONCR_OFFS;
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} else {
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sr_bit = SYSCSR_POFFENB;
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reg_offs = PWROFFCR_OFFS;
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}
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/* Wait until SYSC is ready to accept a power request */
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for (k = 0; k < SYSCSR_RETRIES; k++) {
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if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit))
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break;
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udelay(SYSCSR_DELAY_US);
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}
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if (k == SYSCSR_RETRIES)
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return -EAGAIN;
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/* Submit power shutoff or power resume request */
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iowrite32(BIT(sysc_ch->chan_bit),
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rcar_sysc_base + sysc_ch->chan_offs + reg_offs);
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return 0;
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}
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static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
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{
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unsigned int isr_mask = BIT(sysc_ch->isr_bit);
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unsigned int chan_mask = BIT(sysc_ch->chan_bit);
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unsigned int status;
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unsigned long flags;
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int ret = 0;
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int k;
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spin_lock_irqsave(&rcar_sysc_lock, flags);
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iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
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/* Submit power shutoff or resume request until it was accepted */
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for (k = 0; k < PWRER_RETRIES; k++) {
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ret = rcar_sysc_pwr_on_off(sysc_ch, on);
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if (ret)
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goto out;
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status = ioread32(rcar_sysc_base +
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sysc_ch->chan_offs + PWRER_OFFS);
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if (!(status & chan_mask))
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break;
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udelay(PWRER_DELAY_US);
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}
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if (k == PWRER_RETRIES) {
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ret = -EIO;
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goto out;
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}
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/* Wait until the power shutoff or resume request has completed * */
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for (k = 0; k < SYSCISR_RETRIES; k++) {
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if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask)
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break;
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udelay(SYSCISR_DELAY_US);
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}
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if (k == SYSCISR_RETRIES)
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ret = -EIO;
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iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
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out:
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spin_unlock_irqrestore(&rcar_sysc_lock, flags);
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pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off",
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sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret);
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return ret;
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}
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int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch)
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{
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return rcar_sysc_power(sysc_ch, false);
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}
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int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch)
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{
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return rcar_sysc_power(sysc_ch, true);
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}
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static bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch)
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{
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unsigned int st;
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st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS);
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if (st & BIT(sysc_ch->chan_bit))
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return true;
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return false;
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}
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struct rcar_sysc_pd {
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struct generic_pm_domain genpd;
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struct rcar_sysc_ch ch;
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unsigned int flags;
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char name[0];
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};
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static inline struct rcar_sysc_pd *to_rcar_pd(struct generic_pm_domain *d)
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{
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return container_of(d, struct rcar_sysc_pd, genpd);
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}
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static int rcar_sysc_pd_power_off(struct generic_pm_domain *genpd)
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{
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struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
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pr_debug("%s: %s\n", __func__, genpd->name);
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if (pd->flags & PD_NO_CR) {
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pr_debug("%s: Cannot control %s\n", __func__, genpd->name);
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return -EBUSY;
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}
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if (pd->flags & PD_BUSY) {
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pr_debug("%s: %s busy\n", __func__, genpd->name);
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return -EBUSY;
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}
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return rcar_sysc_power_down(&pd->ch);
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}
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static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd)
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{
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struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
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pr_debug("%s: %s\n", __func__, genpd->name);
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if (pd->flags & PD_NO_CR) {
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pr_debug("%s: Cannot control %s\n", __func__, genpd->name);
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return 0;
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}
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return rcar_sysc_power_up(&pd->ch);
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}
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static bool has_cpg_mstp;
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static void __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
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{
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struct generic_pm_domain *genpd = &pd->genpd;
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const char *name = pd->genpd.name;
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struct dev_power_governor *gov = &simple_qos_governor;
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if (pd->flags & PD_CPU) {
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/*
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* This domain contains a CPU core and therefore it should
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* only be turned off if the CPU is not in use.
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*/
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pr_debug("PM domain %s contains %s\n", name, "CPU");
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pd->flags |= PD_BUSY;
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gov = &pm_domain_always_on_gov;
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} else if (pd->flags & PD_SCU) {
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/*
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* This domain contains an SCU and cache-controller, and
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* therefore it should only be turned off if the CPU cores are
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* not in use.
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*/
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pr_debug("PM domain %s contains %s\n", name, "SCU");
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pd->flags |= PD_BUSY;
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gov = &pm_domain_always_on_gov;
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} else if (pd->flags & PD_NO_CR) {
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/*
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* This domain cannot be turned off.
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*/
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pd->flags |= PD_BUSY;
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gov = &pm_domain_always_on_gov;
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}
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if (!(pd->flags & (PD_CPU | PD_SCU))) {
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/* Enable Clock Domain for I/O devices */
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genpd->flags = GENPD_FLAG_PM_CLK;
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if (has_cpg_mstp) {
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genpd->attach_dev = cpg_mstp_attach_dev;
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genpd->detach_dev = cpg_mstp_detach_dev;
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} else {
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genpd->attach_dev = cpg_mssr_attach_dev;
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genpd->detach_dev = cpg_mssr_detach_dev;
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}
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}
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genpd->power_off = rcar_sysc_pd_power_off;
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genpd->power_on = rcar_sysc_pd_power_on;
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if (pd->flags & (PD_CPU | PD_NO_CR)) {
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/* Skip CPUs (handled by SMP code) and areas without control */
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pr_debug("%s: Not touching %s\n", __func__, genpd->name);
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goto finalize;
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}
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if (!rcar_sysc_power_is_off(&pd->ch)) {
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pr_debug("%s: %s is already powered\n", __func__, genpd->name);
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goto finalize;
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}
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rcar_sysc_power_up(&pd->ch);
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finalize:
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pm_genpd_init(genpd, gov, false);
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}
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static const struct of_device_id rcar_sysc_matches[] = {
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#ifdef CONFIG_ARCH_R8A7779
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{ .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
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#endif
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#ifdef CONFIG_ARCH_R8A7790
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{ .compatible = "renesas,r8a7790-sysc", .data = &r8a7790_sysc_info },
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#endif
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#ifdef CONFIG_ARCH_R8A7791
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{ .compatible = "renesas,r8a7791-sysc", .data = &r8a7791_sysc_info },
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#endif
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#ifdef CONFIG_ARCH_R8A7792
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{ .compatible = "renesas,r8a7792-sysc", .data = &r8a7792_sysc_info },
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#endif
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#ifdef CONFIG_ARCH_R8A7793
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/* R-Car M2-N is identical to R-Car M2-W w.r.t. power domains. */
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{ .compatible = "renesas,r8a7793-sysc", .data = &r8a7791_sysc_info },
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#endif
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#ifdef CONFIG_ARCH_R8A7794
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{ .compatible = "renesas,r8a7794-sysc", .data = &r8a7794_sysc_info },
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#endif
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#ifdef CONFIG_ARCH_R8A7795
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{ .compatible = "renesas,r8a7795-sysc", .data = &r8a7795_sysc_info },
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#endif
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#ifdef CONFIG_ARCH_R8A7796
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{ .compatible = "renesas,r8a7796-sysc", .data = &r8a7796_sysc_info },
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#endif
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{ /* sentinel */ }
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};
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struct rcar_pm_domains {
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struct genpd_onecell_data onecell_data;
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struct generic_pm_domain *domains[RCAR_PD_ALWAYS_ON + 1];
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};
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static int __init rcar_sysc_pd_init(void)
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{
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const struct rcar_sysc_info *info;
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const struct of_device_id *match;
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struct rcar_pm_domains *domains;
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struct device_node *np;
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u32 syscier, syscimr;
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void __iomem *base;
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unsigned int i;
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int error;
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if (rcar_sysc_base)
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return 0;
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np = of_find_matching_node_and_match(NULL, rcar_sysc_matches, &match);
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if (!np)
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return -ENODEV;
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info = match->data;
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has_cpg_mstp = of_find_compatible_node(NULL, NULL,
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"renesas,cpg-mstp-clocks");
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base = of_iomap(np, 0);
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if (!base) {
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pr_warn("%s: Cannot map regs\n", np->full_name);
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error = -ENOMEM;
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goto out_put;
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}
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rcar_sysc_base = base;
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domains = kzalloc(sizeof(*domains), GFP_KERNEL);
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if (!domains) {
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error = -ENOMEM;
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goto out_put;
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}
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domains->onecell_data.domains = domains->domains;
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domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains);
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for (i = 0, syscier = 0; i < info->num_areas; i++)
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syscier |= BIT(info->areas[i].isr_bit);
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/*
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* Mask all interrupt sources to prevent the CPU from receiving them.
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* Make sure not to clear reserved bits that were set before.
|
||
|
|
*/
|
||
|
|
syscimr = ioread32(base + SYSCIMR);
|
||
|
|
syscimr |= syscier;
|
||
|
|
pr_debug("%s: syscimr = 0x%08x\n", np->full_name, syscimr);
|
||
|
|
iowrite32(syscimr, base + SYSCIMR);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* SYSC needs all interrupt sources enabled to control power.
|
||
|
|
*/
|
||
|
|
pr_debug("%s: syscier = 0x%08x\n", np->full_name, syscier);
|
||
|
|
iowrite32(syscier, base + SYSCIER);
|
||
|
|
|
||
|
|
for (i = 0; i < info->num_areas; i++) {
|
||
|
|
const struct rcar_sysc_area *area = &info->areas[i];
|
||
|
|
struct rcar_sysc_pd *pd;
|
||
|
|
|
||
|
|
pd = kzalloc(sizeof(*pd) + strlen(area->name) + 1, GFP_KERNEL);
|
||
|
|
if (!pd) {
|
||
|
|
error = -ENOMEM;
|
||
|
|
goto out_put;
|
||
|
|
}
|
||
|
|
|
||
|
|
strcpy(pd->name, area->name);
|
||
|
|
pd->genpd.name = pd->name;
|
||
|
|
pd->ch.chan_offs = area->chan_offs;
|
||
|
|
pd->ch.chan_bit = area->chan_bit;
|
||
|
|
pd->ch.isr_bit = area->isr_bit;
|
||
|
|
pd->flags = area->flags;
|
||
|
|
|
||
|
|
rcar_sysc_pd_setup(pd);
|
||
|
|
if (area->parent >= 0)
|
||
|
|
pm_genpd_add_subdomain(domains->domains[area->parent],
|
||
|
|
&pd->genpd);
|
||
|
|
|
||
|
|
domains->domains[area->isr_bit] = &pd->genpd;
|
||
|
|
}
|
||
|
|
|
||
|
|
error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
|
||
|
|
|
||
|
|
out_put:
|
||
|
|
of_node_put(np);
|
||
|
|
return error;
|
||
|
|
}
|
||
|
|
early_initcall(rcar_sysc_pd_init);
|
||
|
|
|
||
|
|
void __init rcar_sysc_init(phys_addr_t base, u32 syscier)
|
||
|
|
{
|
||
|
|
u32 syscimr;
|
||
|
|
|
||
|
|
if (!rcar_sysc_pd_init())
|
||
|
|
return;
|
||
|
|
|
||
|
|
rcar_sysc_base = ioremap_nocache(base, PAGE_SIZE);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Mask all interrupt sources to prevent the CPU from receiving them.
|
||
|
|
* Make sure not to clear reserved bits that were set before.
|
||
|
|
*/
|
||
|
|
syscimr = ioread32(rcar_sysc_base + SYSCIMR);
|
||
|
|
syscimr |= syscier;
|
||
|
|
pr_debug("%s: syscimr = 0x%08x\n", __func__, syscimr);
|
||
|
|
iowrite32(syscimr, rcar_sysc_base + SYSCIMR);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* SYSC needs all interrupt sources enabled to control power.
|
||
|
|
*/
|
||
|
|
pr_debug("%s: syscier = 0x%08x\n", __func__, syscier);
|
||
|
|
iowrite32(syscier, rcar_sysc_base + SYSCIER);
|
||
|
|
}
|