263 lines
8.5 KiB
C
263 lines
8.5 KiB
C
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/*
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* drivers/spi/im501.h
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* (C) Copyright 2014-2018
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* Fortemedia, Inc. <www.fortemedia.com>
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* Author: HenryZhang <henryhzhang@fortemedia.com>;
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* LiFu <fuli@fortemedia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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*/
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#ifndef _IM501_H_
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#define _IM501_H_
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#define iM501_I2C_REG 0x10
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#define iM501_SPI_REG 0x01
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/* iM501_I2C_SPI_REG bit2 = 1 means I2C mode, default is SPI mode */
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#define iM501_I2C_SPI_REG 0x12
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#define TO_DSP_CMD_ADDR (0x0FFFBFF8)
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#define TO_DSP_CMD_OFFSET_ATTR(x) ((x) & 0xFFFF)
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#define TO_DSP_CMD_OFFSET_STAT(x) (((x) & 0xFF) << 24)
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#define TO_DSP_CMD_REQ_START_BUF_TRANS 0x19
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#define TO_DSP_CMD_REQ_STOP_BUF_TRANS 0x1D
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#define TO_DSP_CMD_REQ_ENTER_PSM 0x0D
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#define TO_DSP_CMD_REQ_ENTER_NORMAL 0x11
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#define TO_DSP_CMD_REQ_ENTER_BYPASS 0x6D
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//Fuli 20170922 to support SPI recording
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#define TO_DSP_CMD_REQ_SWITCH_SPI_REC 0x59
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//
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#define TO_HOST_CMD_KEYWORD_DET 0x40
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#define TO_HOST_CMD_DATA_BUF_RDY 0x41
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#define TO_DSP_FRAMECOUNTER_ADDR (0x0FFFBEFC)
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#define CHECK_PLL_READY_ADDR (0x0FFFFF34)
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#define TO_HOST_CMD_ADDR (0x0FFFBFFC)
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#define HW_VOICE_BUF_START (0x0FFF3EE0) // DRAM voice buffer : 0x0FFF3EE0 ~ 0x0FFFBEDF = 32kB
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//fuli 20170629 for new protocol of SM501
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#define HW_VOICE_BUF_BANK0 (0x0FFFAEE0)
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#define HW_VOICE_BUF_BANK1 (0x0FFFB6E0)
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#define BANK0 (0x00)
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#define BANK1 (0x01)
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#define BANK0_SYNC (0x02)
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#define BANK1_SYNC (0x03)
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//
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#define HW_VOICE_BUF_BANK_SIZE (1024*2) //2kB
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#define HW_BUF_RX_L (0x0FFFE000) //1kB
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#define HW_BUF_RX_R (0x0FFFE400) //1kB
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#define HW_BUF_RX_SIZE (2048)
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#define TO_HOST_CMD_OFFSET_ATTR(x) ((x) & 0xFFFF)
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#define TO_HOST_CMD_OFFSET_CMD(x) (((x) & 0xFF) << 16)
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#define TO_HOST_CMD_OFFSET_STAT(x) (((x) & 0xFF) << 24)
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#define GET_HOST_CMD_OFFSET_ATTR(x) ((x) & 0xFFFF)
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#define GET_HOST_CMD_OFFSET_CMD(x) (((x)>>16) & 0xFF)
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#define GET_HOST_CMD_OFFSET_STAT(x) (((x)>>24) & 0xFF)
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#define CHECK_LAST_PACK(x) (((x)>>15) & 0x01)
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#define GET_PACK_LEN(x) ((x) & 0x7F)
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#define GET_PACK_INDEX(x) ((x) & 0x7F)
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#define CMD_STAT_INIT 0xFF
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#define CMD_STAT_DONE 0x00
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#define IM501_I2C_CMD_DM_WR 0x2B //dram 2-byte write command, For burst mode, only can be 2 bytes
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#define IM501_I2C_CMD_DM_RD 0x27 //dram rea command d, Normal W/R, can be 1,2,4 bytes.
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#define IM501_I2C_CMD_IM_WR 0x0D //iram 4-byte write command
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#define IM501_I2C_CMD_IM_RD 0x07 //iram read command
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#define IM501_I2C_CMD_REG_WR_1 0x48 //i2c register 1-byte write command
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#define IM501_I2C_CMD_REG_WR_2 0x4A //i2c register 2-byte write command
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#define IM501_I2C_CMD_REG_RD 0x46 //i2c register read command, only support one byte read
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#define IM501_I2C_CMD_DM_WR_BST 0xAB //4a?
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#define IM501_I2C_CMD_DM_RD_BST 0xA7
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#define IM501_I2C_CMD_IM_WR_BST 0x8B
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#define IM501_I2C_CMD_IM_RD_BST 0x87
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#define IM501_SPI_CMD_DM_WR 0x05
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#define IM501_SPI_CMD_DM_RD 0x01
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#define IM501_SPI_CMD_IM_WR 0x04
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#define IM501_SPI_CMD_IM_RD 0x00
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#define IM501_SPI_CMD_REG_WR 0x06
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#define IM501_SPI_CMD_REG_RD 0x02
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#define SUCCESS 0u
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#define NO_ERR 0u
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#define SPI_BUS_ERR 179u
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#define I2C_BUS_ERR 180u
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#define TO_501_CMD_ERR 181u
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#define SPI_FIFO_SIZE (3072)
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#define SPI_BUF_SIZE (1024*2)
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typedef struct to_host_cmd_t {
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unsigned int attri:24;
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unsigned int cmd_byte:7;
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unsigned int status:1;
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} to_host_cmd;
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typedef struct to_im501_cmd_t {
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unsigned int attri:24;
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unsigned int cmd_byte_ext:7;
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unsigned int status:1;
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unsigned char cmd_byte;
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} to_501_cmd;
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typedef struct voice_buf_t {
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unsigned int length;
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unsigned int index;
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unsigned char *pdata;
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unsigned char done;
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} voice_buf;
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/*
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* Henry Zhang - define structure and enum for device_read/device_write operations
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*/
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#define CMD_BUF_LEN 1024
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enum DEV_COMMAND {
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//The long commands
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FM_SMVD_REG_READ, //Command #0
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FM_SMVD_REG_WRITE, //Command #1
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FM_SMVD_DSP_ADDR_READ, //Command #2
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FM_SMVD_DSP_ADDR_WRITE, //Command #3
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FM_SMVD_MODE_SET, //Command #4
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FM_SMVD_MODE_GET, //Command #5
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//The long commands
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FM_SMVD_DSP_BWRITE, //Command #6
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FM_SMVD_VECTOR_GET, //Command #7
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FM_SMVD_REG_DUMP, //Command #8
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FM_SMVD_HOST_IRQQUERY,
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FM_SMVD_DL_EFT_FW,
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FM_SMVD_GET_FW_TYPE,
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FM_SMVD_SWITCH_FW,
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//Fuli 20170922 to support SPI recording
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FM_SMVD_START_SPI_REC,
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FM_SMVD_STOP_SPI_REC,
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//
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//Fuli 20171022 to support general message interface
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FM_SMVD_SEND_MESSAGE,
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// Nvidia commands
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FM_SMVD_ENABLE_HOTWORD_DETECT,
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FM_SMVD_DISABLE_HOTWORD_DETECT
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};
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enum IM501_FW_TYPE {
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IM501_DSP_FW, //MSB
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IM501_EFT_FW, //LSB
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};
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/*
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* The structure dev_cmd_short/long defines the command protocol between the
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* library and the device driver.
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* In device driver, the device read and device write functions handle the
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* structure data and parse it.
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*
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* dev_cmd_short: the structure for device command FM_SMVD_REG_READ,
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* FM_SMVD_REG_WRITE, FM_SMVD_DSP_READ,
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* FM_SMVD_DSP_WRITE, FM_SMVD_MODE_SET and FM_SMVD_MODE_GET, for which no
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* extra data buffer is needed.
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*/
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typedef struct dev_cmd_short_t {
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unsigned short cmd_name; //The commands from #0~#5
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unsigned int addr; //The address of the register or dsp memory for
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//the commands #0~#3, or the dsp mode for #4~#5.
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unsigned int val; //The operation or returned value for the
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//commands #0~#3, or zero for the commands #4~#5.
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unsigned char reserved[6];
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} dev_cmd_short;
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/*
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* dev_cmd_long: the structure for device command FM_SMVD_DSP_BWRITE,
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* FM_SMVD_VECTOR_GET and FM_SMVD_REG_DUMP,
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* for which the extra data buffer is necessary for input or output data.
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*/
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typedef struct dev_cmd_long_t {
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unsigned short cmd_name; //The command from #6~#8
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unsigned int addr; //The address of dsp memory for the command #6,
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//or zero for #7~#8.
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unsigned int val; //The the valid data length.
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unsigned char reserved[6];
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unsigned char buf[CMD_BUF_LEN]; //The data buffer in fixed size,
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//for input and output.
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} dev_cmd_long;
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//Henry Zhang - end of device_read/device_write operation definitions
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//Fuli 20171010 to support SPI recording
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/*if spi speed is fast enough, we can get total data from SPI together
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#define DSP_SPI_REC_CH_NUM 10
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typedef struct dev_cmd_start_rec_t {
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unsigned short cmd_name;
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unsigned short ch_num;
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unsigned char ch_idx[DSP_SPI_REC_CH_NUM];
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unsigned char hd_reserved[2];
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} dev_cmd_start_rec;
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*/
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//
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enum {
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IM501_I2C_CMD_16_WRITE = 1,
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IM501_I2C_CMD_32_READ,
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IM501_I2C_CMD_32_WRITE,
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};
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enum DSP_MODE {
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FM_SMVD_DSP_BYPASS, /* the bypass mode of the dsp. in this mode
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the DMIC input is bypassed to codec. */
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FM_SMVD_DSP_DETECTION,
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FM_SMVD_DSP_MIXTURE,
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FM_SMVD_DSP_FACTORY,
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FM_SMVD_DSP_VR, /* the voice recognition mode of the dsp. */
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FM_SMVD_DSP_CM, /* the communication mode of the dsp. */
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FM_SMVD_DSP_BARGE_IN, /* the barge-in mode of the dsp. in this mode
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FM_SMVD detects the keyword and issues
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interrupt to the host AP. */
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FM_SMVD_GET_DSP_MODE,
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FM_SMVD_DOWNLOAD_UDT_FIRMWARE,
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FM_SMVD_DOWNLOAD_EFT_FIRMWARE,
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FM_SMVD_DOWNLOAD_WHOLE_FIRMWARE,
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FM_SMVD_SET_EFT_SVTHD,
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FM_SMVD_SET_UDT_SVTHD,
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FM_SMVD_DUMP_REGISTER,
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};
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typedef struct dev_cmd_mode_gs_t {
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unsigned short cmd_name;
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unsigned int dsp_mode;
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unsigned char hd_reserved[10];
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} dev_cmd_mode_gs;
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typedef struct dev_cmd_fw_type_t {
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unsigned short cmd_name;
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unsigned int firmware_type;
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unsigned char hd_reserved[10];
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} dev_cmd_fw_type;
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typedef struct dev_cmd_reg_rw_t {
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unsigned short cmd_name;
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unsigned int reg_addr;
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unsigned int reg_val;
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unsigned char hd_reserved[6];
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} dev_cmd_reg_rw;
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typedef struct dev_cmd_fwdl_t {
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unsigned short cmd_name;
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unsigned int dsp_addr;
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unsigned int data_len;
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unsigned char hd_reserved[6];
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unsigned char buf[1024];
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} dev_cmd_fwdl;
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//Fuli 20171022 to support general message interface
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typedef struct dev_cmd_message_t {
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unsigned short cmd_name;
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unsigned char message_index;
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unsigned int message_data;
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} dev_cmd_message;
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//
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#endif /* _IM501_H_ */
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