174 lines
4.1 KiB
C
174 lines
4.1 KiB
C
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/*
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* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* Freescale DIU Frame Buffer device driver
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*
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* Authors: Hongjun Chen <hong-jun.chen@freescale.com>
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* Paul Widmer <paul.widmer@freescale.com>
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* Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
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* York Sun <yorksun@freescale.com>
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*
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* Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef __FSL_DIU_FB_H__
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#define __FSL_DIU_FB_H__
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#include <linux/types.h>
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struct mfb_chroma_key {
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int enable;
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__u8 red_max;
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__u8 green_max;
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__u8 blue_max;
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__u8 red_min;
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__u8 green_min;
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__u8 blue_min;
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};
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struct aoi_display_offset {
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__s32 x_aoi_d;
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__s32 y_aoi_d;
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};
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#define MFB_SET_CHROMA_KEY _IOW('M', 1, struct mfb_chroma_key)
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#define MFB_SET_BRIGHTNESS _IOW('M', 3, __u8)
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#define MFB_SET_ALPHA _IOW('M', 0, __u8)
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#define MFB_GET_ALPHA _IOR('M', 0, __u8)
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#define MFB_SET_AOID _IOW('M', 4, struct aoi_display_offset)
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#define MFB_GET_AOID _IOR('M', 4, struct aoi_display_offset)
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#define MFB_SET_PIXFMT _IOW('M', 8, __u32)
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#define MFB_GET_PIXFMT _IOR('M', 8, __u32)
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/*
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* The MPC5121 BSP comes with a gamma_set utility that initializes the
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* gamma table. Unfortunately, it uses bad values for the IOCTL commands,
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* but there's nothing we can do about it now. These ioctls are only
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* supported on the MPC5121.
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*/
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#define MFB_SET_GAMMA _IOW('M', 1, __u8)
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#define MFB_GET_GAMMA _IOR('M', 1, __u8)
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/*
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* The original definitions of MFB_SET_PIXFMT and MFB_GET_PIXFMT used the
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* wrong value for 'size' field of the ioctl. The current macros above use the
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* right size, but we still need to provide backwards compatibility, at least
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* for a while.
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*/
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#define MFB_SET_PIXFMT_OLD 0x80014d08
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#define MFB_GET_PIXFMT_OLD 0x40014d08
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#ifdef __KERNEL__
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/*
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* These are the fields of area descriptor(in DDR memory) for every plane
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*/
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struct diu_ad {
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/* Word 0(32-bit) in DDR memory */
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/* __u16 comp; */
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/* __u16 pixel_s:2; */
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/* __u16 pallete:1; */
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/* __u16 red_c:2; */
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/* __u16 green_c:2; */
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/* __u16 blue_c:2; */
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/* __u16 alpha_c:3; */
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/* __u16 byte_f:1; */
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/* __u16 res0:3; */
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__be32 pix_fmt; /* hard coding pixel format */
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/* Word 1(32-bit) in DDR memory */
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__le32 addr;
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/* Word 2(32-bit) in DDR memory */
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/* __u32 delta_xs:11; */
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/* __u32 res1:1; */
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/* __u32 delta_ys:11; */
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/* __u32 res2:1; */
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/* __u32 g_alpha:8; */
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__le32 src_size_g_alpha;
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/* Word 3(32-bit) in DDR memory */
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/* __u32 delta_xi:11; */
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/* __u32 res3:5; */
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/* __u32 delta_yi:11; */
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/* __u32 res4:3; */
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/* __u32 flip:2; */
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__le32 aoi_size;
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/* Word 4(32-bit) in DDR memory */
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/*__u32 offset_xi:11;
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__u32 res5:5;
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__u32 offset_yi:11;
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__u32 res6:5;
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*/
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__le32 offset_xyi;
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/* Word 5(32-bit) in DDR memory */
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/*__u32 offset_xd:11;
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__u32 res7:5;
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__u32 offset_yd:11;
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__u32 res8:5; */
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__le32 offset_xyd;
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/* Word 6(32-bit) in DDR memory */
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__u8 ckmax_r;
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__u8 ckmax_g;
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__u8 ckmax_b;
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__u8 res9;
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/* Word 7(32-bit) in DDR memory */
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__u8 ckmin_r;
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__u8 ckmin_g;
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__u8 ckmin_b;
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__u8 res10;
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/* __u32 res10:8; */
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/* Word 8(32-bit) in DDR memory */
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__le32 next_ad;
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/* Word 9(32-bit) in DDR memory, just for 64-bit aligned */
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__u32 paddr;
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} __attribute__ ((packed));
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/* DIU register map */
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struct diu {
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__be32 desc[3];
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__be32 gamma;
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__be32 pallete;
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__be32 cursor;
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__be32 curs_pos;
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__be32 diu_mode;
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__be32 bgnd;
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__be32 bgnd_wb;
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__be32 disp_size;
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__be32 wb_size;
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__be32 wb_mem_addr;
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__be32 hsyn_para;
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__be32 vsyn_para;
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__be32 syn_pol;
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__be32 thresholds;
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__be32 int_status;
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__be32 int_mask;
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__be32 colorbar[8];
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__be32 filling;
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__be32 plut;
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} __attribute__ ((packed));
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/*
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* Modes of operation of DIU. The DIU supports five different modes, but
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* the driver only supports modes 0 and 1.
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*/
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#define MFB_MODE0 0 /* DIU off */
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#define MFB_MODE1 1 /* All three planes output to display */
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#endif /* __KERNEL__ */
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#endif /* __FSL_DIU_FB_H__ */
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