375 lines
13 KiB
C
375 lines
13 KiB
C
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#ifndef __LINUX_GPIO_DRIVER_H
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#define __LINUX_GPIO_DRIVER_H
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#include <linux/device.h>
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#include <linux/types.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/lockdep.h>
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#include <linux/pinctrl/pinctrl.h>
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struct gpio_desc;
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struct of_phandle_args;
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struct device_node;
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struct seq_file;
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struct gpio_device;
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struct module;
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enum gpiod_flags;
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#ifdef CONFIG_GPIOLIB
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/**
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* enum single_ended_mode - mode for single ended operation
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* @LINE_MODE_PUSH_PULL: normal mode for a GPIO line, drive actively high/low
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* @LINE_MODE_OPEN_DRAIN: set line to be open drain
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* @LINE_MODE_OPEN_SOURCE: set line to be open source
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*/
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enum single_ended_mode {
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LINE_MODE_PUSH_PULL,
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LINE_MODE_OPEN_DRAIN,
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LINE_MODE_OPEN_SOURCE,
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};
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/**
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* struct gpio_chip - abstract a GPIO controller
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* @label: a functional name for the GPIO device, such as a part
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* number or the name of the SoC IP-block implementing it.
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* @gpiodev: the internal state holder, opaque struct
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* @parent: optional parent device providing the GPIOs
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* @owner: helps prevent removal of modules exporting active GPIOs
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* @request: optional hook for chip-specific activation, such as
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* enabling module power and clock; may sleep
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* @free: optional hook for chip-specific deactivation, such as
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* disabling module power and clock; may sleep
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* @get_direction: returns direction for signal "offset", 0=out, 1=in,
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* (same as GPIOF_DIR_XXX), or negative error
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* @direction_input: configures signal "offset" as input, or returns error
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* @direction_output: configures signal "offset" as output, or returns error
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* @timestamp_control: enables signal "offset" for timestamping
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* @timestamp_read: read timestamp value for given signal "offset"
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* @get: returns value for signal "offset", 0=low, 1=high, or negative error
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* @set: assigns output value for signal "offset"
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* @set_multiple: assigns output values for multiple signals defined by "mask"
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* @set_debounce: optional hook for setting debounce time for specified gpio in
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* interrupt triggered gpio chips
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* @set_single_ended: optional hook for setting a line as open drain, open
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* source, or non-single ended (restore from open drain/source to normal
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* push-pull mode) this should be implemented if the hardware supports
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* open drain or open source settings. The GPIOlib will otherwise try
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* to emulate open drain/source by not actively driving lines high/low
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* if a consumer request this. The driver may return -ENOTSUPP if e.g.
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* it supports just open drain but not open source and is called
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* with LINE_MODE_OPEN_SOURCE as mode argument.
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* @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
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* implementation may not sleep
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* @dbg_show: optional routine to show contents in debugfs; default code
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* will be used when this is omitted, but custom code can show extra
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* state (such as pullup/pulldown configuration).
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* @base: identifies the first GPIO number handled by this chip;
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* or, if negative during registration, requests dynamic ID allocation.
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* DEPRECATION: providing anything non-negative and nailing the base
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* offset of GPIO chips is deprecated. Please pass -1 as base to
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* let gpiolib select the chip base in all possible cases. We want to
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* get rid of the static GPIO number space in the long run.
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* @ngpio: the number of GPIOs handled by this controller; the last GPIO
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* handled is (base + ngpio - 1).
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* @names: if set, must be an array of strings to use as alternative
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* names for the GPIOs in this chip. Any entry in the array
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* may be NULL if there is no alias for the GPIO, however the
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* array must be @ngpio entries long. A name can include a single printk
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* format specifier for an unsigned int. It is substituted by the actual
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* number of the gpio.
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* @can_sleep: flag must be set iff get()/set() methods sleep, as they
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* must while accessing GPIO expander chips over I2C or SPI. This
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* implies that if the chip supports IRQs, these IRQs need to be threaded
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* as the chip access may sleep when e.g. reading out the IRQ status
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* registers.
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* @irq_not_threaded: flag must be set if @can_sleep is set but the
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* IRQs don't need to be threaded
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* @read_reg: reader function for generic GPIO
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* @write_reg: writer function for generic GPIO
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* @pin2mask: some generic GPIO controllers work with the big-endian bits
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* notation, e.g. in a 8-bits register, GPIO7 is the least significant
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* bit. This callback assigns the right bit mask.
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* @reg_dat: data (in) register for generic GPIO
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* @reg_set: output set register (out=high) for generic GPIO
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* @reg_clk: output clear register (out=low) for generic GPIO
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* @reg_dir: direction setting register for generic GPIO
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* @bgpio_bits: number of register bits used for a generic GPIO i.e.
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* <register width> * 8
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* @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
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* shadowed and real data registers writes together.
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* @bgpio_data: shadowed data register for generic GPIO to clear/set bits
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* safely.
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* @bgpio_dir: shadowed direction register for generic GPIO to clear/set
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* direction safely.
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* @irqchip: GPIO IRQ chip impl, provided by GPIO driver
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* @irqdomain: Interrupt translation domain; responsible for mapping
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* between GPIO hwirq number and linux irq number
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* @irq_base: first linux IRQ number assigned to GPIO IRQ chip (deprecated)
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* @irq_handler: the irq handler to use (often a predefined irq core function)
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* for GPIO IRQs, provided by GPIO driver
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* @irq_default_type: default IRQ triggering type applied during GPIO driver
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* initialization, provided by GPIO driver
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* @irq_parent: GPIO IRQ chip parent/bank linux irq number,
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* provided by GPIO driver
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* @irq_need_valid_mask: If set core allocates @irq_valid_mask with all
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* bits set to one
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* @irq_valid_mask: If not %NULL holds bitmask of GPIOs which are valid to
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* be included in IRQ domain of the chip
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* @lock_key: per GPIO IRQ chip lockdep class
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*
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* A gpio_chip can help platforms abstract various sources of GPIOs so
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* they can all be accessed through a common programing interface.
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* Example sources would be SOC controllers, FPGAs, multifunction
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* chips, dedicated GPIO expanders, and so on.
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*
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* Each chip controls a number of signals, identified in method calls
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* by "offset" values in the range 0..(@ngpio - 1). When those signals
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* are referenced through calls like gpio_get_value(gpio), the offset
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* is calculated by subtracting @base from the gpio number.
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*/
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struct gpio_chip {
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const char *label;
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struct gpio_device *gpiodev;
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struct device *parent;
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struct module *owner;
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int (*request)(struct gpio_chip *chip,
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unsigned offset);
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void (*free)(struct gpio_chip *chip,
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unsigned offset);
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int (*get_direction)(struct gpio_chip *chip,
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unsigned offset);
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int (*direction_input)(struct gpio_chip *chip,
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unsigned offset);
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int (*direction_output)(struct gpio_chip *chip,
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unsigned offset, int value);
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int (*timestamp_control)(struct gpio_chip *chip,
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unsigned offset, int enable);
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int (*timestamp_read)(struct gpio_chip *chip,
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unsigned offset, u64 *ts);
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int (*get)(struct gpio_chip *chip,
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unsigned offset);
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void (*set)(struct gpio_chip *chip,
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unsigned offset, int value);
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void (*set_multiple)(struct gpio_chip *chip,
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unsigned long *mask,
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unsigned long *bits);
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int (*set_debounce)(struct gpio_chip *chip,
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unsigned offset,
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unsigned debounce);
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int (*set_single_ended)(struct gpio_chip *chip,
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unsigned offset,
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enum single_ended_mode mode);
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int (*suspend_configure)(struct gpio_chip *chip,
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unsigned offset,
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enum gpiod_flags dflags);
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int (*is_enabled)(struct gpio_chip *chip,
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unsigned offset);
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int (*to_irq)(struct gpio_chip *chip,
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unsigned offset);
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void (*dbg_show)(struct seq_file *s,
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struct gpio_chip *chip);
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int base;
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u16 ngpio;
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const char *const *names;
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bool can_sleep;
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bool irq_not_threaded;
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#if IS_ENABLED(CONFIG_GPIO_GENERIC)
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unsigned long (*read_reg)(void __iomem *reg);
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void (*write_reg)(void __iomem *reg, unsigned long data);
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unsigned long (*pin2mask)(struct gpio_chip *gc, unsigned int pin);
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void __iomem *reg_dat;
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void __iomem *reg_set;
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void __iomem *reg_clr;
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void __iomem *reg_dir;
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int bgpio_bits;
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spinlock_t bgpio_lock;
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unsigned long bgpio_data;
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unsigned long bgpio_dir;
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#endif
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#ifdef CONFIG_GPIOLIB_IRQCHIP
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/*
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* With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
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* to handle IRQs for most practical cases.
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*/
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struct irq_chip *irqchip;
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struct irq_domain *irqdomain;
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unsigned int irq_base;
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irq_flow_handler_t irq_handler;
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unsigned int irq_default_type;
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int irq_parent;
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bool irq_need_valid_mask;
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unsigned long *irq_valid_mask;
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struct lock_class_key *lock_key;
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#endif
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#if defined(CONFIG_OF_GPIO)
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/*
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* If CONFIG_OF is enabled, then all GPIO controllers described in the
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* device tree automatically may have an OF translation
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*/
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struct device_node *of_node;
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int of_gpio_n_cells;
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int (*of_xlate)(struct gpio_chip *gc,
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const struct of_phandle_args *gpiospec, u32 *flags);
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#endif
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};
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extern const char *gpiochip_is_requested(struct gpio_chip *chip,
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unsigned offset);
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/* add/remove chips */
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extern int gpiochip_add_data(struct gpio_chip *chip, void *data);
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static inline int gpiochip_add(struct gpio_chip *chip)
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{
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return gpiochip_add_data(chip, NULL);
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}
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extern void gpiochip_remove(struct gpio_chip *chip);
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extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip,
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void *data);
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extern void devm_gpiochip_remove(struct device *dev, struct gpio_chip *chip);
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extern struct gpio_chip *gpiochip_find(void *data,
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int (*match)(struct gpio_chip *chip, void *data));
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/* lock/unlock as IRQ */
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int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
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void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
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bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);
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/* Line status inquiry for drivers */
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bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
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bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);
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/* get driver data */
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void *gpiochip_get_data(struct gpio_chip *chip);
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struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
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struct bgpio_pdata {
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const char *label;
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int base;
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int ngpio;
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};
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#if IS_ENABLED(CONFIG_GPIO_GENERIC)
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int bgpio_init(struct gpio_chip *gc, struct device *dev,
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unsigned long sz, void __iomem *dat, void __iomem *set,
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void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
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unsigned long flags);
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#define BGPIOF_BIG_ENDIAN BIT(0)
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#define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
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#define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
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#define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
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#define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
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#define BGPIOF_NO_OUTPUT BIT(5) /* only input */
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#endif
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#ifdef CONFIG_GPIOLIB_IRQCHIP
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void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
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struct irq_chip *irqchip,
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int parent_irq,
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irq_flow_handler_t parent_handler);
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int _gpiochip_irqchip_add(struct gpio_chip *gpiochip,
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struct irq_chip *irqchip,
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unsigned int first_irq,
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irq_flow_handler_t handler,
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unsigned int type,
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struct lock_class_key *lock_key);
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#ifdef CONFIG_LOCKDEP
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#define gpiochip_irqchip_add(...) \
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( \
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({ \
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static struct lock_class_key _key; \
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_gpiochip_irqchip_add(__VA_ARGS__, &_key); \
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}) \
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)
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#else
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#define gpiochip_irqchip_add(...) \
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_gpiochip_irqchip_add(__VA_ARGS__, NULL)
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#endif
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#endif /* CONFIG_GPIOLIB_IRQCHIP */
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int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
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void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);
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#ifdef CONFIG_PINCTRL
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/**
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* struct gpio_pin_range - pin range controlled by a gpio chip
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* @head: list for maintaining set of pin ranges, used internally
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* @pctldev: pinctrl device which handles corresponding pins
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* @range: actual range of pins controlled by a gpio controller
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*/
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struct gpio_pin_range {
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struct list_head node;
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struct pinctrl_dev *pctldev;
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struct pinctrl_gpio_range range;
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};
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int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
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unsigned int gpio_offset, unsigned int pin_offset,
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unsigned int npins);
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int gpiochip_add_pingroup_range(struct gpio_chip *chip,
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struct pinctrl_dev *pctldev,
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unsigned int gpio_offset, const char *pin_group);
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void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
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#else
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static inline int
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gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
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unsigned int gpio_offset, unsigned int pin_offset,
|
||
|
|
unsigned int npins)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
static inline int
|
||
|
|
gpiochip_add_pingroup_range(struct gpio_chip *chip,
|
||
|
|
struct pinctrl_dev *pctldev,
|
||
|
|
unsigned int gpio_offset, const char *pin_group)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void
|
||
|
|
gpiochip_remove_pin_ranges(struct gpio_chip *chip)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* CONFIG_PINCTRL */
|
||
|
|
|
||
|
|
struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
|
||
|
|
const char *label);
|
||
|
|
void gpiochip_free_own_desc(struct gpio_desc *desc);
|
||
|
|
|
||
|
|
#else /* CONFIG_GPIOLIB */
|
||
|
|
|
||
|
|
static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
|
||
|
|
{
|
||
|
|
/* GPIO can never have been requested */
|
||
|
|
WARN_ON(1);
|
||
|
|
return ERR_PTR(-ENODEV);
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* CONFIG_GPIOLIB */
|
||
|
|
|
||
|
|
#endif
|