161 lines
4.6 KiB
C
161 lines
4.6 KiB
C
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/*
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* include/linux/irqchip/tegra-t18x-agic.h
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*
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* Header file for managing AGIC interrupt controller
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*
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* Copyright (C) 2015-2016 NVIDIA Corporation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _TEGRA_T18X_AGIC_H_
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#define _TEGRA_T18X_AGIC_H_
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/* INT_T18x_ADMA Channel End of Transfer Interrupt */
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#define INT_T18x_AGIC_START 32
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#define INT_T18x_ADMA_EOT0 32
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#define INT_T18x_ADMA_EOT1 33
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#define INT_T18x_ADMA_EOT2 34
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#define INT_T18x_ADMA_EOT3 35
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#define INT_T18x_ADMA_EOT4 36
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#define INT_T18x_ADMA_EOT5 37
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#define INT_T18x_ADMA_EOT6 38
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#define INT_T18x_ADMA_EOT7 39
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#define INT_T18x_ADMA_EOT8 40
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#define INT_T18x_ADMA_EOT9 41
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#define INT_T18x_ADMA_EOT10 42
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#define INT_T18x_ADMA_EOT11 43
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#define INT_T18x_ADMA_EOT12 44
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#define INT_T18x_ADMA_EOT13 45
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#define INT_T18x_ADMA_EOT14 46
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#define INT_T18x_ADMA_EOT15 47
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#define INT_T18x_ADMA_EOT16 48
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#define INT_T18x_ADMA_EOT17 49
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#define INT_T18x_ADMA_EOT18 50
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#define INT_T18x_ADMA_EOT19 51
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#define INT_T18x_ADMA_EOT20 52
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#define INT_T18x_ADMA_EOT21 53
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#define INT_T18x_ADMA_EOT22 54
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#define INT_T18x_ADMA_EOT23 55
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#define INT_T18x_ADMA_EOT24 56
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#define INT_T18x_ADMA_EOT25 57
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#define INT_T18x_ADMA_EOT26 58
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#define INT_T18x_ADMA_EOT27 59
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#define INT_T18x_ADMA_EOT28 60
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#define INT_T18x_ADMA_EOT29 61
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#define INT_T18x_ADMA_EOT30 62
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#define INT_T18x_ADMA_EOT31 63
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/* AMISC Mailbox Full Interrupts */
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#define INT_T18x_AMISC_MBOX_FULL0 64
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#define INT_T18x_AMISC_MBOX_FULL1 65
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#define INT_T18x_AMISC_MBOX_FULL2 66
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#define INT_T18x_AMISC_MBOX_FULL3 67
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#define INT_T18x_AMISC_MBOX_FULL4 68
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#define INT_T18x_AMISC_MBOX_FULL5 69
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#define INT_T18x_AMISC_MBOX_FULL6 70
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#define INT_T18x_AMISC_MBOX_FULL7 71
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/* AMISC Mailbox Empty Interrupts */
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#define INT_T18x_AMISC_MBOX_EMPTY0 72
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#define INT_T18x_AMISC_MBOX_EMPTY1 73
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#define INT_T18x_AMISC_MBOX_EMPTY2 74
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#define INT_T18x_AMISC_MBOX_EMPTY3 75
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#define INT_T18x_AMISC_MBOX_EMPTY4 76
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#define INT_T18x_AMISC_MBOX_EMPTY5 77
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#define INT_T18x_AMISC_MBOX_EMPTY6 78
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#define INT_T18x_AMISC_MBOX_EMPTY7 79
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/* AHSP SHARED INTERRUPT */
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#define INT_T18x_AHSP_SHRD0 80
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#define INT_T18x_AHSP_SHRD1 81
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#define INT_T18x_AHSP_SHRD2 82
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#define INT_T18x_AHSP_SHRD3 83
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#define INT_T18x_AHSP_SHRD4 84
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/* ADSP/PTM Performance Monitoring Unit Interrupt */
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#define INT_T18x_ADSP_PMU 85
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/* ADSP Watchdog Timer Reset Request */
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#define INT_T18x_ADSP_WDT 86
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/* ADSP L2 Cache Controller Interrupt */
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#define INT_T18x_ADSP_L2CC 87
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/* AHUB Error Interrupt */
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#define INT_T18x_AHUB_ERR 88
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/* AMC Error Interrupt */
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#define INT_T18x_AMC_ERR 89
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/* INT_T18x_ADMA Error Interrupt */
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#define INT_T18x_ADMA_ERR0 90
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#define INT_T18x_ADMA_ERR1 91
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#define INT_T18x_ADMA_ERR2 92
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#define INT_T18x_ADMA_ERR3 93
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/* ADSP Standby WFI. ADSP in idle mode. Waiting for Interrupt */
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#define INT_T18x_WFI 94
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/* ADSP Standby WFE. ADSP in idle mode. Waiting for Event */
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#define INT_T18x_WFE 95
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#define INT_T18x_ADSP_CTI 96
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/* Activity monitoring on ADSP. This interrupt is from AMISC */
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#define INT_T18x_ADSP_ACTMON 97
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#define INT_T18x_ADSP_ACTMON_RESERVED0 98
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#define INT_T18x_ADSP_ACTMON_RESERVED1 99
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/* LIC to APE Interrupts */
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#define INT_T18x_LIC_TO_APE0 100
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#define INT_T18x_LIC_TO_APE1 101
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/* VI Notify High Interrupt */
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#define INT_T18x_VI_NOTIFY_HIGH 102
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#define INT_T18x_VI_NOTIFY_LOW 103
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/* I2C {1,3,8} Interrupt */
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#define INT_T18x_I2C_IRQ1 104
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#define INT_T18x_I2C_IRQ3 105
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#define INT_T18x_I2C_IRQ8 106
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/* System Door Bell interrupt */
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#define INT_T18x_SHSP2APE_DB 107
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/* Top WDT FIQ interrupt */
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#define INT_T18x_TOP_WDT_FIQ 108
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/* Top WDT IRQ interrupt */
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#define INT_T18x_TOP_WDT_IRQ 109
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/* ATKE Timer IRQ interrupt */
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#define INT_T18x_ATKE_TMR0 110
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#define INT_T18x_ATKE_TMR1 111
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#define INT_T18x_ATKE_TMR2 112
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#define INT_T18x_ATKE_TMR3 113
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/* ATKE WDT FIQ interrupt */
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#define INT_T18x_ATKE_WDT_FIQ 114
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/* ATKE WDT IRQ interrupt */
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#define INT_T18x_ATKE_WDT_IRQ 115
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/* ATKE WDT error interrupt */
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#define INT_T18x_ATKE_WDT_ERR 116
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/* UART interrupt to AGIC (In FPGA platform only) */
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#define INT_T18x_UART_FPGA 117
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#define INT_T18x_AGIC_END 117
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#endif /* _TEGRA_T18X_AGIC_H_ */
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