109 lines
3.3 KiB
C
109 lines
3.3 KiB
C
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/*
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* include/linux/irqchip/tegra-t210-agic.h
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*
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* Header file for managing AGIC interrupt controller
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*
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* Copyright (C) 2014-2015 NVIDIA Corporation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _TEGRA_T210_AGIC_H_
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#define _TEGRA_T210_AGIC_H_
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/* AMISC Mailbox Full Interrupts */
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#define INT_T210_AGIC_START 32
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#define INT_T210_AMISC_MBOX_FULL0 32
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#define INT_T210_AMISC_MBOX_FULL1 33
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#define INT_T210_AMISC_MBOX_FULL2 34
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#define INT_T210_AMISC_MBOX_FULL3 35
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/* AMISC Mailbox Empty Interrupts */
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#define INT_T210_AMISC_MBOX_EMPTY0 36
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#define INT_T210_AMISC_MBOX_EMPTY1 37
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#define INT_T210_AMISC_MBOX_EMPTY2 38
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#define INT_T210_AMISC_MBOX_EMPTY3 39
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/* AMISC CPU Arbitrated Semaphore Interrupt */
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#define INT_T210_AMISC_CPU_ARB_SEMA0 40
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#define INT_T210_AMISC_CPU_ARB_SEMA1 41
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#define INT_T210_AMISC_CPU_ARB_SEMA2 42
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#define INT_T210_AMISC_CPU_ARB_SEMA3 43
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#define INT_T210_AMISC_CPU_ARB_SEMA4 44
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#define INT_T210_AMISC_CPU_ARB_SEMA5 45
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#define INT_T210_AMISC_CPU_ARB_SEMA6 46
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#define INT_T210_AMISC_CPU_ARB_SEMA7 47
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/* AMISC ADSP Arbitrated Semaphore Interrupt */
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#define INT_T210_AMISC_ADSP_ARB_SEMA0 48
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#define INT_T210_AMISC_ADSP_ARB_SEMA1 49
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#define INT_T210_AMISC_ADSP_ARB_SEMA2 50
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#define INT_T210_AMISC_ADSP_ARB_SEMA3 51
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#define INT_T210_AMISC_ADSP_ARB_SEMA4 52
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#define INT_T210_AMISC_ADSP_ARB_SEMA5 53
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#define INT_T210_AMISC_ADSP_ARB_SEMA6 54
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#define INT_T210_AMISC_ADSP_ARB_SEMA7 55
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/* INT_T210_ADMA Channel End of Transfer Interrupt */
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#define INT_T210_ADMA_EOT0 56
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#define INT_T210_ADMA_EOT1 57
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#define INT_T210_ADMA_EOT2 58
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#define INT_T210_ADMA_EOT3 59
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#define INT_T210_ADMA_EOT4 60
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#define INT_T210_ADMA_EOT5 61
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#define INT_T210_ADMA_EOT6 62
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#define INT_T210_ADMA_EOT7 63
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#define INT_T210_ADMA_EOT8 64
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#define INT_T210_ADMA_EOT9 65
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#define INT_T210_ADMA_EOT10 66
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#define INT_T210_ADMA_EOT11 67
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#define INT_T210_ADMA_EOT12 68
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#define INT_T210_ADMA_EOT13 69
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#define INT_T210_ADMA_EOT14 70
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#define INT_T210_ADMA_EOT15 71
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#define INT_T210_ADMA_EOT16 72
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#define INT_T210_ADMA_EOT17 73
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#define INT_T210_ADMA_EOT18 74
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#define INT_T210_ADMA_EOT19 75
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#define INT_T210_ADMA_EOT20 76
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#define INT_T210_ADMA_EOT21 77
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/* ADSP/PTM Performance Monitoring Unit Interrupt */
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#define INT_T210_ADSP_PMU 78
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/* ADSP Watchdog Timer Reset Request */
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#define INT_T210_ADSP_WDT 79
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/* ADSP L2 Cache Controller Interrupt */
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#define INT_T210_ADSP_L2CC 80
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/* AHUB Error Interrupt */
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#define INT_T210_AHUB_ERR 81
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/* AMC Error Interrupt */
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#define INT_T210_AMC_ERR 82
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/* INT_T210_ADMA Error Interrupt */
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#define INT_T210_ADMA_ERR 83
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/* ADSP Standby WFI. ADSP in idle mode. Waiting for Interrupt */
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#define INT_T210_WFI 84
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/* ADSP Standby WFE. ADSP in idle mode. Waiting for Event */
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#define INT_T210_WFE 85
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/* AMISC Actmon interrupt */
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#define INT_T210_ADSP_ACTMON 87
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#define INT_T210_AGIC_END 87
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#endif /* _TEGRA_T210_AGIC_H_ */
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