191 lines
4.9 KiB
C
191 lines
4.9 KiB
C
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/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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* Copyright (C) 2015-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef LINUX_MMC_CQ_HCI_H
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#define LINUX_MMC_CQ_HCI_H
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#include <linux/mmc/core.h>
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#define CQE_BASE 0xF000
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#define CQE_RES_SZ 0x100
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/* registers */
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#define CQVER 0x00
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#define CQCAP 0x04
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#define CQCFG 0x08
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#define CQ_DCMD 0x00001000
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#define CQ_TASK_DESC_SZ 0x00000100
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#define CQ_ENABLE 0x00000001
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#define CQCTL 0x0C
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#define CLEAR_ALL_TASKS 0x00000100
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#define HALT 0x00000001
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#define CQIS 0x10
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#define CQISTE 0x14
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#define CQISGE 0x18
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#define CQIC 0x1C
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#define CQTDLBA 0x20
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#define CQTDLBAU 0x24
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#define CQTDBR 0x28
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#define CQTCN 0x2C
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#define CQDQS 0x30
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#define CQDPT 0x34
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#define CQTCLR 0x38
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#define CQSSC1 0x40
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#define CQSSC2 0x44
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#define CQCRDCT 0x48
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#define CQRMEM 0x50
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#define CQTERRI 0x54
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#define CQTERRI_DATA_XFER_ERR_TASK_ID_SHIFT 24
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#define CQTERRI_DATA_XFER_ERR_TASK_ID_MASK 0x1F000000
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#define CQTERRI_RESP_ERR_TASK_ID_SHIFT 8
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#define CQTERRI_RESP_ERR_TASK_ID_MASK 0x1F00
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#define CQCRI 0x58
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#define CQCRA 0x5C
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#define CQIC_ENABLE (1 << 31)
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#define CQIC_RESET (1 << 16)
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#define CQIC_ICCTHWEN (1 << 15)
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#define CQIC_ICCTH(x) ((x & 0x1F) << 8)
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#define CQIC_ICC_TH (1 << 8)
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#define CQIC_ICTOVALWEN (1 << 7)
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#define CQIC_ICTOVAL(x) (x & 0x7F)
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#define CQIS_HAC (1 << 0)
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#define CQIS_TCC (1 << 1)
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#define CQIS_RED (1 << 2)
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#define CQIS_TCL (1 << 3)
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#define CQ_INT_EN (0x3 << 14)
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#define CQ_INT_ALL 0xF
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#define CQIC_DEFAULT_ICCTH 31
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#define CQIC_DEFAULT_ICTOVAL 1
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#define CQIC_MAX_ICTOVAL 0x7F
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/* attribute fields */
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#define VALID(x) ((x & 1) << 0)
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#define END(x) ((x & 1) << 1)
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#define INT(x) ((x & 1) << 2)
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#define ACT(x) ((x & 0x7) << 3)
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/* data command task descriptor fields */
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#define FORCED_PROG(x) ((x & 1) << 6)
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#define CONTEXT(x) ((x & 0xF) << 7)
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#define DATA_TAG(x) ((x & 1) << 11)
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#define DATA_DIR(x) ((x & 1) << 12)
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#define PRIORITY(x) ((x & 1) << 13)
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#define QBAR(x) ((x & 1) << 14)
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#define REL_WRITE(x) ((x & 1) << 15)
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#define BLK_COUNT(x) ((x & 0xFFFF) << 16)
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#define BLK_ADDR(x) ((x & 0xFFFFFFFF) << 32)
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/* direct command task descriptor fields */
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#define CMD_INDEX(x) ((x & 0x3F) << 16)
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#define CMD_TIMING(x) ((x & 1) << 22)
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#define RESP_TYPE(x) ((x & 0x3) << 23)
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/* transfer descriptor fields */
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#define DAT_LENGTH(x) ((x & 0xFFFF) << 16)
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#define DAT_ADDR_LO(x) ((x & 0xFFFFFFFF) << 32)
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#define DAT_ADDR_HI(x) ((x & 0xFFFFFFFF) << 0)
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struct cmdq_host {
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const struct cmdq_host_ops *ops;
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void __iomem *mmio;
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struct mmc_host *mmc;
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/* 64 bit DMA */
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bool dma64;
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int num_slots;
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u32 dcmd_slot;
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u32 caps;
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#define CMDQ_TASK_DESC_SZ_128 0x1
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u32 quirks;
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#define CMDQ_QUIRK_SHORT_TXFR_DESC_SZ (1<<0)
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#define CMDQ_QUIRK_NO_DCMD (1<<1)
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#define CMDQ_QUIRK_CQIC_SUPPORT (1<<2)
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/* Set CMD_TIMING bit to 1 for R1B DCMDs */
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#define CMDQ_QUIRK_SET_CMD_TIMING_R1B_DCMD (1<<3)
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bool enabled;
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bool halted;
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bool init_done;
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u64 *desc_base;
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/* total descriptor size */
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u8 slot_sz;
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/* 64/128 bit depends on CQCFG */
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u8 task_desc_len;
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/* 64 bit on 32-bit arch, 128 bit on 64-bit */
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u8 link_desc_len;
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u64 *trans_desc_base;
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/* same length as transfer descriptor */
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u8 trans_desc_len;
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dma_addr_t desc_dma_base;
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dma_addr_t trans_desc_dma_base;
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struct completion halt_comp;
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spinlock_t cmdq_lock;
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struct mmc_request **mrq_slot;
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struct mmc_data *data; /* Current data request */
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size_t desc_size;
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size_t data_size;
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void *private;
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};
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struct cmdq_host_ops {
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void (*set_tranfer_params)(struct mmc_host *mmc);
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void (*set_data_timeout)(struct mmc_host *mmc, u32 val);
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void (*clear_set_irqs)(struct mmc_host *mmc, u32 clear, u32 set);
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void (*dump_vendor_regs)(struct mmc_host *mmc);
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void (*write_l)(struct cmdq_host *host, u32 val, int reg);
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u32 (*read_l)(struct cmdq_host *host, int reg);
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void (*runtime_pm_get)(struct mmc_host *mmc);
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void (*runtime_pm_put)(struct mmc_host *mmc);
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};
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static inline void cmdq_writel(struct cmdq_host *host, u32 val, int reg)
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{
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if (unlikely(host->ops->write_l))
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host->ops->write_l(host, val, reg);
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else
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writel(val, host->mmio + reg);
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}
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static inline u32 cmdq_readl(struct cmdq_host *host, int reg)
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{
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if (unlikely(host->ops->read_l))
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return host->ops->read_l(host, reg);
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else
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return readl(host->mmio + reg);
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}
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extern irqreturn_t cmdq_irq(struct mmc_host *mmc, u32 intmask);
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extern int cmdq_init(struct cmdq_host *cq_host, struct mmc_host *mmc,
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bool dma64);
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extern int cmdq_reenable(struct mmc_host *mmc);
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extern struct cmdq_host *cmdq_pltfm_init(struct platform_device *pdev);
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#endif
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